WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 44

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
DIGITAL TO ANALOGUE CONVERTER (DAC)
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The WM8900 DACs receive digital input data from the DACDAT pin and via the digital sidetone
path. The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit
digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which
convert them to high quality analogue audio signals. The multi-bit DAC architecture reduces high
frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique
for high linearity and low distortion.
The analogue outputs from the DACs can then be mixed with other analogue inputs using the
output mixers. This mix is fed to the output drivers for headphone or line outputs.
The DACs are enabled by the DACL_ENA and DACR_ENA register bits as defined in Table 27.
The DAC output stage bias current can be optimised by the DAC_BIAS register bits. Note that the
optimum setting for minimum power consumption is not the power-on default value.
Table 27 DAC Enable Control
DAC DIGITAL VOLUME CONTROL
The output level of each DAC can be controlled digitally over a range from–71.625dB to 0dB in
0.375dB steps. The level of attenuation for an eight-bit code X is given by:
0.375 × (X-192) dB for 1 ≤ X ≤ 192;
The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the
DACL_VOL or DACR_VOL control data will be loaded into the respective control register, but will
not actually change the digital gain setting. Both left and right gain settings are updated when a 1
is written to DAC_VU. This makes it possible to update the gain of both channels simultaneously.
Table 28 Digital Volume Control
R3 (03h)
Power
Management 3
R115 (73h)
Output Bias
Control
R11 (0Bh)
Left DAC
Digital Volume
R12 (0Ch)
Right DAC
Digital Volume
REGISTER
ADDRESS
REGISTER
ADDRESS
8
7:0
8
7:0
BIT
1
0
2:1
BIT
DAC_VU
DACL_VOL
[7:0]
DAC_VU
DACR_VOL
[7:0]
DACL_ENA
DACR_ENA
DAC_BIAS
[1:0]
LABEL
LABEL
MUTE for X = 0
0
0
00
0
11000000
(0dB)
0
11000000
(0dB)
DEFAULT
DEFAULT
0dB for 192 ≤ X ≤ 255
Left DAC Enable
0 = DAC disabled
1 = DAC enabled
Right DAC Enable
0 = DAC disabled
1 = DAC enabled
Adjusts DAC bias
00 = Full bias
01 = Half bias (recommended)
10 = Reserved
11 = Reserved
DAC Volume Update
Writing a 1 to this bit will cause left
and right DAC volume to be updated
simultaneously
Left DAC Digital Volume
(See Table 29 for volume range)
DAC Volume Update
Writing a 1 to this bit will cause left
and right DAC volume to be updated
simultaneously
Right DAC Digital Volume
(See Table 29 for volume range)
PD, August 2008, Rev 4.0
DESCRIPTION
DESCRIPTION
Production Data
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