WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 63

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
GENERAL PURPOSE INPUT/OUTPUT
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The WM8900 has three dual purpose input/output pins which may be configured according to the
selected control mode and according to GPIO register settings. The three pins are as follows:
Two analogue inputs may also be configured as headphone jack detect inputs, by use of some of
the same GPIO register fields. These two inputs are as listed below. The default configuration for
these pins is to be analogue inputs.
The ADCLRC/GPIO pin can be configured as a left/right frame clock for the ADC, a headphone
jack detect input, or as one of a number of GPIO output functions. The configuration of this pin as
ADCLRC or as GPIO is determined by the ADCLRC_FN bit.
During power-up, if the MODE pin is low, the serial interface mode of operation is selected as 2
wire, in this case CSB is sampled in order to select the correct device address according to Table
69. Thereafter, the normal CSB function is not required in 2-wire control mode, and the CSB pin is
automatically configured as one of the GPIO functions.
In 3-wire control mode, the MODE pin may be configured as GPIO by register bit MODE_FN. (See
“Control Interface” for further details of this bit.)
The GPIO function of the pin (or pins) selected as GPIO is controlled by the ADCLRC_SRC
register. It is possible for more than one of the GPIO pins to output the same function
simultaneously. The polarity of the GPIO output may be inverted by setting the ADCLRC_INV bit. If
headphone jack detect input is selected, then only one of the possible sources may be selected as
the jack detect input; the chosen input will be determined by the JD_SRC field. (See “Headphone
Jack Detect” for further details of this bit.)
Table 49 GPIO Control
The slow clock must be enabled when using the Jack Detect function. This is used to de-bounce
the jack detect input. See “Headphone Jack Detect” for further details of the associated controls.
The temperature sensor must be enabled for the ‘Temperature ok’ GPIO output to function
properly. See “Thermal Shutdown” for further details.
The SYSCLK GPIO output is derived from SYSCLK and also set by a programmable divider
OPCLK_DIV. See “Clocking and Sample Rates” for further details of this field.
R5 (05h)
Audio
Interface 2
R18 (12h)
GPIO Control
REGISTER
ADDRESS
•
•
•
•
•
ADCLRC/GPIO - ADC Left/Right frame clock or GPIO pin
CSB - Control Interface control or GPIO pin
MODE - Control Interface control or GPIO pin
LINPUT3/JD2 - Analogue input or headphone detect input
RINPUT3/JD3 - Analogue input or headphone detect input
6
7
6:4
BIT
ADCLRC_FN
ADCLRC_INV
ADCLRC_SRC
[2:0]
LABEL
0
0
000
DEFAULT
ADCLRC/GPIO Pin Function Select
0 = ADCLRC frame clock for ADC
1 = GPIO pin
GPIO Output Polarity Invert
0 = Non inverted
1 = Inverted
GPIO Pin Function Select:
000 = Jack detect input
001 = Reserved
010 = Temperature ok
011 = Debounced jack detect output
100 = SYSCLK output
101 = FLL lock
110 = Logic 0
111 = Logic 1
PD, August 2008, Rev 4.0
DESCRIPTION
WM8900
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