WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 64

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
DIGITAL AUDIO INTERFACE
w
Figure 25 Master Mode
Note: The ADC and DAC can run at different sample rates
WM8900
CODEC
The digital audio interface is used for inputting DAC data into the WM8900 and outputting ADC
data from it. It uses five pins:
The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8900 operates as a
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).
ADCLRC can also be configured as a GPIO pin. In this case, the ADC will use DACLRC as a
frame clock. The ADCLRC/GPIO pin function should not be modified while the ADC is enabled.
Four different audio data formats are supported:
All four of these modes are MSB first. They are described in the “Audio Data Formats” section
below. Refer to the “Electrical Characteristics” section for timing information.
Time division multiplexing (TDM) is available in all four data format modes. The WM8900 can be
programmed to send and receive data in one of two time slots.
MASTER AND SLAVE MODE OPERATION
The WM8900 can be configured as either a master or slave mode device. As a master device the
WM8900 generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data
transfer on ADCDAT and DACDAT. In slave mode, the WM8900 responds with data to clocks it
receives over the digital audio interface. The mode can be selected by writing to the BCLK_DIR,
ADCLRC_DIR and DACLRC_DIR register bits. Master and slave modes are illustrated below.
Note that the WM8900 also supports mixed master and slave modes - see “Audio Interface
Control”.
OPERATION WITH ADCLRC AS GPIO
When the ADCLRC/GPIO pin is configured as a GPIO pin (ADCLRC_FN = 1), the DACLRC pin is
used as a frame clock for ADCs and DACs as shown below. The ADCs and DACs must operate at
the same sample rate in this mode. See “General Purpose Input/Output” section for details of
GPIO pin configuration.
•
•
•
•
•
•
•
•
•
ADCLRC
DACLRC
ADCDAT
DACDAT
BCLK
ADCDAT: ADC data output
ADCLRC: ADC data alignment clock
DACDAT: DAC data input
DACLRC: DAC data alignment clock
BCLK: Bit clock, for synchronisation
Left justified
Right justified
I2S
DSP mode
ENCODER/
DECODER
DSP
Figure 26 Slave Mode
Note: The ADC and DAC can run at different sample rates
WM8900
CODEC
ADCLRC
DACLRC
ADCDAT
DACDAT
BCLK
PD, August 2008, Rev 4.0
ENCODER/
DECODER
DSP
Production Data
64