WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 65

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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Note: The ADC and DAC cannot run at different sample rates in this mode
Figure 27 Master Mode with ADCLRC as GPIO
WM8900
CODEC
The Audio Interface output control is illustrated above. The left-right clock control bits,
ADCLRC_DIR and DACLRC_DIR, determine whether the corresponding clock output is enabled
(see “Audio Interface Control” for the definition of these bits). The ADCLRC_FN register bit controls
the mode of operation of the ADCLRC/GPIO pin (see “GPIO” for the definition of this bit).
OPERATION WITH TDM
The digital audio interface on WM8900 has the facility of tri-stating the ADCDAT pin to allow
multiple data sources on the same bus. Time division multiplexing (TDM) is also supported,
allowing audio output data to be transferred simultaneously from two different sources. The
WM8900 ADCs and DACs support TDM in master and slave modes, on both interfaces, and for all
data formats and word lengths.
TDM is enabled using register bits AIFADC_TDM and AIFDAC_TDM. The TDM data slot is
programmed using register bits AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN. (See “Audio
Interface Control” for the definition of these bits.)
When operating in TDM mode with another device, the possible connections are as follows:
Figure 29 TDM with WM8900 as Master
DACLRC
ADCDAT
DACDAT
WM8900
or similar
WM8900
CODEC
GPIO
BCLK
ADCLRC
DACLRC
ADCDAT
DACDAT
ADCLRC
DACLRC
ADCDAT
DACDAT
BCLK
BCLK
ADCLRC
ENCODER/
DECODER
DSP
Processor
Note: The ADC and DAC cannot run at different sample rates in this mode
Figure 28 Slave Mode with ADCLRC as
GPIO
WM8900
CODEC
ADCLRC
DACLRC
Figure 30 TDM with Other CODEC as Master
Or similar
WM8900
ADCDAT
DACDAT
CODEC
WM8900
BCLK
GPIO
ADCLRC
DACLRC
ADCDAT
DACDAT
ADCLRC
DACLRC
ADCDAT
DACDAT
BCLK
BCLK
PD, August 2008, Rev 4.0
ENCODER/
DECODER
DSP
WM8900
Processor
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