WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 75

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
CLOCKING AND SAMPLE RATES
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Notes:
Clocks for the ADCs, DACs, DSP core functions, the digital audio interface and the Ground-
Referenced Headphone output driver are all derived from a common internal clock source,
SYSCLK.
SYSCLK can either be derived directly from MCLK, or may be generated from an FLL using MCLK
or DACLRC as an external reference. The SYSCLK source is selected by MCLK_SRC. Many
commonly-used audio sample rates can be derived directly from typical MCLK frequencies; the
FLL provides additional flexibility for a wider range of MCLK or DACLRC frequencies.
The ADC and DAC sample rates are independently selectable, relative to SYSCLK, using
ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the required sampling
frequency and depending upon the selected clocking mode. Two clocking modes are provided -
Normal mode allows selection of the commonly used sample rates from typical audio system
clocking frequencies (eg. 12.288MHz); USB mode allows many of these sample rates to be
generated from a 12MHz USB clock. Depending on the available clock sources, the USB mode
may be used to save power by supporting 44.1kHz operation without recourse to the FLL.
In Normal mode,
In USB mode,
The above equations determine the required values for ADC_CLKDIV and DAC_CLKDIV. The
clocking mode is selected via the AIF_LRCLKRATE field.
In master mode, BCLK is also derived from SYSCLK via a programmable division set by
BCLK_DIV. In the case where the ADCs and DACs are operating at different sample rates, BCLK
must be set according to whichever is the faster rate. In Master Mode, internal clock divide and
phase control mechanisms ensure that the BCLK, ADCLRC and DACLRC edges will occur in a
predictable and repeatable position relative to each other and to the data for a given combination
of ADC/DAC sample rates and BCLK settings. In Slave Mode, the host processor must ensure that
BCLK, ADCLRC and DACLRC are fully synchronised; if these inputs are not synchronised,
unpredictable pops and noise may result.
Changing the clocking or sample rates on the WM8900 may result in audible pops and clicks. It is
recommended that the amplifier mute control bits are used to enable/disable the analogue outputs
whenever a change is made to any of the clocking or sample rates. The mute control bits for
specific amplifier stages within the WM8900 are detailed in the applicable sections within this
datasheet. Detailed information is available for specific requirements - see “Applications
Information”.
When the ADCLRC/GPIO pin is configured as a GPIO, a clock derived from SYSCLK may be
output on this pin to provide clocking for other parts of the system. The frequency of this signal is
set by OPCLK_DIV.
A slow clock derived from SYSCLK may be used to provide de-bouncing of the headphone detect
function, and to set the timeout period for volume updates when zero-cross functions are used.
This clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
1.
2.
3.
Master Mode: ADC and DAC left/right clocks must be connected together externally, or be of
the same frequency and completely synchronised, when using LOOPBACK function
(ADCLRC_FN=1)
Slave Mode: It is recommended to set ADCLRC_FN = 1 as well, otherwise ADCLRC and
DACLRC must be running at the same BCLK rate and in phase.
When Loopback is enabled simultaneously to the Digital Sidetone, ADC data will be mixed
with DAC data through both signal paths.
ADC_SYSCLK = 256 x ADC Sampling Frequency
DAC_SYSCLK = 256 x DAC Sampling Frequency
ADC_SYSCLK = 272 x ADC Sampling Frequency
DAC_SYSCLK = 272 x DAC Sampling Frequency
PD, August 2008, Rev 4.0
WM8900
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