WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 77

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WM8900LGEFK/RV

Manufacturer Part Number
WM8900LGEFK/RV
Description
Audio CODECs Ultra Low Power Hi-Fi CODEC
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8900LGEFK/RV

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 56 SYSCLK Control
ADC / DAC SAMPLE RATES
The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the
register fields ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the
SYSCLK frequency, and according to the selected mode of operation (Normal or USB). The
applicable fields are described in Table 57.
Selection of USB mode enables a 12MHz USB clock to be used to generate the required internal
clock signals. Table 58 describes the available sample rates using four different common MCLK
frequencies. The AIF_LRCLKRATE field must be set as described in Table 57 to ensure correct
operation of internal functions according to the SYSCLK / Fs ratio.
In Normal mode, the programmable division set by ADC_CLKDIV must ensure that ADC_SYSCLK
is 256 * ADC Sampling Frequency. DAC_CLKDIV must ensure that DAC_SYSCLK is 256 * DAC
Sampling Frequency.
There are constraints on the SYSCLK frequency when using the headphone output. SYSCLK
should be maintained according to the electrical characteristics shown in Table 1, to maintain
output power.
In USB mode, ADC_CLKDIV must ensure that ADC_SYSCLK is 272 * ADC Sampling Frequency.
DAC_CLKDIV must ensure that DAC_SYSCLK is 272 * DAC Sampling Frequency.
Table 57 ADC / DAC Sample Rate Control
R6 (06h)
Clocking 1
R10 (0Ah)
DAC
Control
R7 (07h)
Clocking 2
REGISTER
ADDRESS
REGISTER
ADDRESS
10
7:5
4:2
BIT
8
BIT
AIF_LRCLKRATE
ADC_CLKDIV
[2:0]
DAC_CLKDIV
[2:0]
MCLK_SRC
LABEL
LABEL
0
000
000
0
DEFAULT
DEFAULT
Mode Select
1 = USB mode (272 * Fs)
0 = Normal mode (256 * Fs)
ADC Sample rate divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
DAC Sample rate divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
Clock Source selection
0 = SYSCLK derived from MCLK
1 = SYSCLK derived from FLL output
PD, August 2008, Rev 4.0
DESCRIPTION
DESCRIPTION
WM8900
77

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