WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 80

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WM8900LGEFK/RV

Manufacturer Part Number
WM8900LGEFK/RV
Description
Audio CODECs Ultra Low Power Hi-Fi CODEC
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8900LGEFK/RV

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Quantity
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Part Number:
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Manufacturer:
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20 000
WM8900
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Table 60 BCLK Divider in Master Mode
ADCLRC / DACLRC CONTROL
In Master Mode, ADCLRC and DACLRC are derived from BCLK via programmable dividers set by
ADCLRC_RATE and DACLRC_RATE. The BCLK frequency is derived from SYSCLK according to
BCLK_DIV, as described earlier in Table 59. The definitions of ADCLRC_RATE and
DACLRC_RATE are described in Table 61.
In Slave Mode, ADCLRC and DACLRC are generated externally and appear as an input to the
CODEC.
See “Digital Audio Interface” for details of Master/Salve operation. See “Audio Interface Control” for
further details of how ADCLRC and DACLRC are configured as input or output.
Table 61 ADCLRC / DACLRC Control
OPCLK CONTROL
When the ADCLRC/GPIO pin is configured as a GPIO, a clock derived from SYSCLK may be
output on this pin to provide clocking for other parts of the system. The frequency of this signal is
derived from SYSCLK and determined by OPCLK_DIV, as described in Table 62.
This output of this clock is dependent upon the ADCLRC_SRC register settings described under
“General Purpose Input/Output”.
R8 (08h)
Audio
Interface 3
R9 (09h)
Audio
Interface 4
REGISTER
ADDRESS
SYSCLK
10:0
10:0
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 32
1111 = SYSCLK / 32
BIT
BCLK DIVIDER
BCLK_DIV
ADCLRC_RATE
[10:0]
DACLRC_RATE
[10:0]
LABEL
040h
040h
2.052655
1.8816
1.4112
1.026327
0.9408
0.7056
0.513164
0.4704
0.3528
0.3528
0.3528
(MASTER MODE)
DEFAULT
BCLK RATE
(MHz)
ADCLRC Frequency (Master Mode).
BCLK is divided by this integer.
ADCLRC_RATE is an 11-bit integer
(LSB = 1).
Valid range is 8 .. 2047
DACLRC Frequency (Master Mode).
BCLK is divided by this integer.
DACLRC_RATE is an 11-bit integer
(LSB = 1).
Valid range is 8 .. 2047
PD, August 2008, Rev 4.0
20
20
16
8
8
8
N/A
N/A
N/A
N/A
N/A
MAXIMUM WORD LENGTH
DESCRIPTION
Production Data
80

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