WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 81

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
FLL
w
Table 62 OPCLK Control
SLOWCLK CONTROL
A slow clock derived from SYSCLK may be generated for de-bouncing of the headphone detect
function or to set the timeout period for volume updates when zero-cross functions are used. This
clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE, as described in Table
46 in the “Headphone Jack Detect” section.
The integrated FLL can be used to generate SYSCLK from a wide variety of different reference
sources and frequencies. The FLL can uses MCLK as its reference, which may be a high
frequency (e.g. 13 MHz) reference. The FLL is tolerant of jitter and may be used to generate a
stable SYSCLK from a less stable input signal. The FLL characteristics are summarised in
“Electrical Characteristics”.
The analogue and digital portions of the FLL may be enabled independently via FLL_OSC_ENA
and FLL_ENA. When initialising the FLL, the analogue circuit must be enabled first by setting
FLL_OSC_ENA. The digital circuit may then be enabled on the next register write or later. When
changing FLL settings, it is recommended that the digital circuit be disabled via FLL_ENA and then
re-enabled after the other register settings have been updated. When changing the input reference
frequency F
recommended that the analogue circuit should remain enabled throughout any change of FLL
settings.
The FLL output frequency is directly determined from FLL_FRATIO, FLLCLK_DIV and the real
number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the
fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by
the field FLL_FRACN_ENA. De-selection of fractional mode results in lower power consumption.
The FLL frequency is determined according to the following equation:
F
according to the desired output F
Table 63 Choice of FLLCLK_DIV
Note that the output frequencies that do not lie within the ranges quoted above cannot be
guaranteed across the full range of device operating temperatures.
VCO
R6 (06h)
Clocking 1
2.8125 MHz - 3.125 MHz
5.625 MHz - 6.25 MHz
11.25 MHz - 12.5 MHz
OUTPUT FREQUENCY F
REGISTER
ADDRESS
must be in the range 90-100 MHz. The value of FLLCLK_DIV should be selected as follows
F
F
OUT
VCO
REF
= F
, it is recommended that the FLL be reset by setting FLL_ENA to 0. It is
= (F
REF
14:12
VCO
BIT
x (N + K) x FLL_FRATIO
/ FLLCLK_DIV)
OPCLK_DIV
[2:0]
OUT
OUT
LABEL
.
4h (divide by 32)
3h (divide by 16)
2h (divide by 8)
FLLCLK_DIV
000
DEFAULT
OPCLK Frequency (GPIO function)
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 5.5
101 = SYSCLK / 6
110 = Reserved
111 = Reserved
PD, August 2008, Rev 4.0
DESCRIPTION
WM8900
81