WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 82

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
w
When setting up the FLL, after the register write to enable the FLL (FLL_ENA = 1), the FLL output
clock will be available after the FLL lock time has elapsed. The FLL lock time is the time from last
CSB edge of the serial interface write to first clock edge of f
specified in Table 1. The FLL lock status can be monitored using a GPIO pin, see Table 49.
The register fields that control the FLL are described in Table 64. Example settings for a variety of
reference frequencies and output frequencies are shown in Table 65.
Table 64 FLL Register Map
R1 (01h)
Power
Management 1
R36 (24h)
FLL Control 1
R37 (25h)
FLL Control 2
R38 (26h)
FLL Control 3
R39 (27h)
FLL Control 4
R40 (28h)
FLL Control 5
R41 (29h)
FLL Control 6
REGISTER
ADDRESS
6
8
4:0
8
7:0
7:0
4:0
8:6
4:0
8
7
BIT
FLL_ENA
FLL_OSC_ENA
FLL_FRATIO
[4:0]
FLL_FRACN_E
NA
FLL_K [15:8]
FLL_K [7:0]
FLL_N [9:5]
FLLCLK_DIV
[2:0]
FLL_N [4:0]
FLL_SLOW_L
OCK_REF
LRCLK_REF_E
NA
LABEL
DEFAULT
0
0
8h
0
0h
0h
0Bh
3h
17h
1
0
OUT
FLL Digital Enable
0 = Power down
1 = Power up
FLL_OSC_ENA must be enabled
before enabling FLL_ENA. The
order is important.
Analogue enable
0 = FLL disabled
1 = FLL enabled
FLL_OSC_ENA must be enabled
before enabling FLL_ENA. The
order is important.
CLK_VCO is divided by this
integer, valid from 1 .. 31.
Value 1 recommended for
Reference clock > 96kHz
Value 8 recommended for
Reference clock < 96kHz
Fractional enable
0 = Integer Mode
1 = Fractional Mode
Fractional multiply for CLK_REF
(Most Significant Bits)
Fractional multiply for CLK_REF
(Least Significant Bits)
Integer multiply for CLK_REF
(Most Significant Bits)
F
000 = F
001 = F
010 = F
011 = F
100 = F
101-111 = Reserved
Integer multiply for CLK_REF
(Least Significant Bits)
Low frequency reference locking
0 = Lock achieved after 509 ref
clks (Recommended for Reference
clock > 48kHz)
1 = Lock achieved after 49 ref clks
(Recommended for Reference
clock <= 48kHz)
FLL reference clock input selector
0 = MCLK
1 = DACLRC
OUT
from FLL. The FLL lock time is
clock divider
PD, August 2008, Rev 4.0
VCO
VCO
VCO
VCO
VCO
DESCRIPTION
/ 2
/ 4
/ 8 (best performance)
/ 16
/ 32
Production Data
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