WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 84

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
CONTROL INTERFACE
w
The WM8900 is controlled by writing to registers through a serial control interface. The interface
may be either a 2-wire or 3-wire configuration.
SELECTION OF CONTROL MODE
At power-up, the MODE pin determines which control mode is selected, as described in Table 66.
An internal pull-up causes default selection of 3-wire mode.
Table 66 Control Interface Mode Selection
In 3-wire mode, the MODE pin can also be used as GPIO. To achieve this, the MODE_FN register
bit must be set to 1. This causes the WM8900 to select 3-wire mode regardless of the MODE pin.
Note that GPIO is not supported on the MODE pin in 2-wire mode and setting MODE_FN to 1 has
no effect in 2-wire mode. Therefore, 3-wire mode must be initially selected as per Table 66 before
writing to MODE_FN to select the GPIO function.
The MODE pull-up can be enabled / disabled by register bit MODE_PU_ENA. When using the
MODE pin as a GPIO output, it may be desirable to disable the pull-up to reduce power
consumption. The value of MODE_PU_ENA has no effect on Mode selection when 3-wire mode
has been selected by setting MODE_FN to 1.
The register bits that determine the 2-wire or 3-wire mode selection are described in Table 67. See
“General Purpose Input/Output” for more details on the use of the MODE pin as GPIO.
Table 67 MODE Pin Function Control
3-WIRE CONTROL MODE
3-wire mode uses the CSB, SCLK and SDIN pins on the WM8900. In 3-wire mode, every rising
edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a
complete control word consisting of the last 16 bits.
In 3-wire mode, the data comprises 24 bits in total. The first bit is the read/write (R/W) bit. This is
followed by 7 address bits (A6 to A0), which identify the register to be accessed. The remaining 16
bits (B15 to B0) are data bits, corresponding to the 16 bits in the WM8900 register.
The following timing diagram shows the supported read and write implementation in 3 wire mode.
Figure 47 3-Wire Serial Control Timing
R18 (12h)
GPIO
Control
REGISTER
ADDRESS
High (default)
MODE
Low
12
11
BIT
MODE_PU_ENA
MODE_FN
LABEL
INTERFACE FORMAT
2 wire
3 wire
1
0
DEFAULT
Enables the MODE Pull-Up resistor
0 = MODE Pull-Up disabled
1 = MODE Pull-Up enabled
Selects Interface Control Mode
0 = MODE pin selects 2-wire mode
when low and 3-wire mode when high.
1 = Interface operates in 3-wire mode
regardless of the MODE pin. MODE can
be an input or output under the control of
the GPIO control register.
PD, August 2008, Rev 4.0
DESCRIPTION
Production Data
84