WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 86

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
READBACK IN 2-WIRE MODE
w
In 2-wire mode, Auto-Incremental Write operations are supported. In this type of transfer, additional
bytes of data (B15-B8 and B7-B0) are transmitted in sequence without the need to re-transmit the
device address or register address. The WM8900 automatically increments the register address for
each additional set of data bits received. This continues until the controlling device indicates the
transfer is complete by a rising edge on SDIN while SCLK is held high. Auto-Incremental Writes
are enabled by default; this can be set by the user as described in Table 70.
Table 70 2-Wire Interface Control
Readback is supported from the registers listed in Table 68.
The controller indicates the START of data transfer with a high to low transition on SDIN while
SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-
wire bus respond to the START condition and shift in the next eight bits on SDIN (7-bit address,
MSB first + Read/Write bit = 0). Hence the first byte should equal 0x34 or 0x36. If the device
address received matches the address of the WM8900 (configured by the CSB pin on power up),
then the WM8900 responds by pulling SDIN low on the next clock pulse (ACK). If the address is
not recognised the WM8900 returns to the idle condition and waits for a new start condition and
valid device address.
During a read, once the WM8900 has acknowledged a correct device address, the controller sends
the WM8900 register address (MSB first). The WM8900 then acknowledges the register address
byte by pulling SDIN low for one clock pulse. The controller then issues a repeated START with a
high to low transition on SDIN while SCLK remains high. The controller then sends the WM8900
device read address (7-bit address, MSB first + Read/Write bit = 1). Hence this byte should equal
0x35 or 0x37. If the device address received matches the address of the WM8900 (configured by
the CSB pin on power up), then the WM8900 responds by pulling SDIN low on the next clock pulse
(ACK). If the address is not recognised the WM8900 returns to the idle condition and waits for a
new start condition and valid device address.
During the next 9 SCLK cycles from the controller, WM8900 clocks out register data (bits 15-8,
MSB first) on the first 8 cycles, and on the 9
During the next 9 SCLK cycles from the controller, WM8900 clocks out register data (bits 7-0, MSB
first) on the first 8 cycles, and on the 9
Transfers are complete when there is a low to high transition on SDIN while SCLK is high (STOP).
After a complete sequence the WM8900 returns to the idle state and waits for another start
condition. If a START or STOP condition is detected out of sequence at any point during data
transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
Figure 49 2-Wire Serial Control Interface Reads
R18 (12h)
GPIO Control
REGISTER
ADDRESS
15
13
BIT
AUTO_INC
CSB_PD_ENA
LABEL
th
SCLK cycle, the controller responds by pulling SDIN low.
th
cycle, the controller responds by pulling SDIN low.
1
1
DEFAULT
Auto-Incremental write enable
0 = Auto-Incremental writes
disabled
1 = Auto-Incremental writes
enabled
Enables the CSB Pull-Down
resistor
0 = CSB Pull-Down disabled
1 = CSB Pull-Down enabled
PD, August 2008, Rev 4.0
DESCRIPTION
Production Data
86