WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 89

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
STOPPING THE MASTER CLOCK
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In order to minimise power consumed in the digital core of the WM8900, the master clock may be
stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the
SYSCLK_ENA bit (R2, bit 15) can be set to stop the MCLK signal from propagating into the device
core. In Standby mode, setting SYSCLK_ENA will typically provide an additional power saving on
DCVDD of 20uA. However, since setting SYSCLK_ENA has no effect on the power consumption
of other system components external to the WM8900, it is preferable to disable the master clock at
its source wherever possible. Figure 46 on page 76 shows the clock distribution within WM8900.
MCLK should not be stopped while the Headphone outputs are enabled, as this would prevent the
charge pump from functioning.
Table 73 Stopping the Master Clock
Note:
Before SYSCLK_ENA can be set, the control bits ADCL_ENA, ADCR_ENA, DACL_ENA and
DACR_ENA must be set to zero and a waiting time of 1ms must be observed. Any failure to follow
this procedure may prevent DACs and ADCs from re-starting correctly.
R2 (02h)
Power
Management 2
REGISTER
ADDRESS
15
BIT
SYSCLK_ENA
LABEL
0
DEFAULT
Master clock disable
0 = Master clock disabled
1 = Master clock enabled
PD, August 2008, Rev 4.0
DESCRIPTION
WM8900
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