WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 90

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
REGISTER MAP
w
(10h)
(11h)
(12h)
(15h)
(16h)
(17h)
REG
(Ah)
(Bh)
(Ch)
(Dh)
(Eh)
(0h)
(1h)
(2h)
(3h)
(4h)
(5h)
(6h)
(7h)
(8h)
(9h)
R10
R11
R12
R13
R14
R15
(Fh)
R16
R17
R18
R21
R22
R23
R24
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
PWR MGMT (1)
PWR MGMT (2) SYSCL
PWR MGMT (3)
INTERFACE (1)
INTERFACE (2)
INTERFACE (3)
INTERFACE (4)
CLOCKING (1)
CLOCKING (2)
JACK DETECT
INPUT BOOST
DIGITAL SIDE
RIGHT INPUT
INPUT CTRL
LEFT INPUT
RIGHT DAC
RIGHT ADC
DAC CTRL
ADC CTRL
GPIOCTRL
LEFT DAC
LEFT ADC
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
DIGITAL
DIGITAL
DIGITAL
DIGITAL
RESET
AUDIO
AUDIO
AUDIO
AUDIO
NAME
TONE
CTRL
K_ENA
CL_SR
DACL_
AUTO_
AIFAD
SRC
INC
15
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CR_SR
DACR_
CHIP_REV[3:0]
AIFAD
SRC
14
C
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OPCLK_DIV[2:0]
CSB_P
D_ENA
AIFAD
AIFDA
C_TD
C_TD
13
M
M
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAC_S
K_RAT
_PU_E
MODE
AIFAD
M_CH
AIFDA
M_CH
DMCL
C_TD
C_TD
AIF_T
AN
AN
NA
12
RI
E
0
0
0
0
0
0
0
0
0
0
0
0
0
ADCL_DAC_SVOL[3:0]
ADCLR
DACLR
DAC_BOOST[1:
MODE
C_DIR
C_DIR
_FN
JD_EN1[5:0]
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0]
AIF_LR
CLKRA
TE
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
JD_EN
MONO
DAC_
SW_RESET_CHIP_ID[15:0]
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
START
AS_EN
MCLK_
DAC_S
DAC_V
DAC_V
ADC_H
ADC_V
ADC_V
JD_MO
L_ENA
OUT1_
FB_EN
B_FILT
PF_EN
OUtT1
MICB_
IN_VU INL_Z
IN_VU INR_Z
UP_BI
AIF_B
CLK_I
SRC
LVL
NV
DE
A
A
U
U
A
U
U
0
0
0
8
ADCR_DAC_SVOL[3:0]
OUT1R
CP_EN
AIF_LR
ADCLR
C_INV
CLK_I
MUTE
_ENA
DAC_
RATE
NV
A
C
C
0
0
0
0
0
0
7
ADC_CLKDIV[2:0]
0
ADCLR
ADC_HPF_CUT
IN1L_E
OUT2L
INR_M
FLL_E
MODE
INL_M
DAC_
MUTE
_ENA
C_FN
ADCLRC_RATE[10:0]
DACLRC_RATE[10:0]
UTE
UTE
AIF_WL[1:0]
NA
NA
ADCLRC_SRC[2:0]
0
0
0
6
IN3L_BOOST[2:0]
[1:0]
MIXINL
OUT2R
IN2L_E
_ENA
_ENA
DEEMP[1:0]
NA
0
0
0
0
0
5
R_ENA
DAC_C
DACR_VOL[7:0]
ADCR_VOL[7:0]
IN3L_E
MICB_
DACL_VOL[7:0]
ADCL_VOL[7:0]
MIXIN
OMP
AIF_FMT[1:0]
ENA
NA
0
0
0
DAC_CLKDIV[2:0]
4
MIXOU
DAC_C
ADC_TO_DACL
TL_EN
OMPM
BIAS_
INL_E
BCLK_DIV[3:0]
ODE
ENA
JD_EN0[5:0]
NA
A
0
0
0
0
3
INR_VOL[4:0]
INL_VOL[4:0]
[1:0]
JD_SRC[2:0]
PD, August 2008, Rev 4.0
BUF_E
MIXOU
TR_EN
ADC_C
VMID_
INR_E
MUTE
IN1R_
DAC_
OMP
ENA
NA
NA
A
0
0
2
IN2L_BOOST[2:0]
VMID_MODE[1:
ADCL_
DACL_
ADC_C
TOCLK
_RATE
DACL_
ADCL_
OMPM
DATIN
DATIN
IN2R_
ADC_TO_DAC
ENA
ENA
ODE
ENA
V
V
0
1
R[1:0]
Production Data
0]
ADCR_
DACR_
DACR_
ADCR_
BCLK_
TOCLK
TEMP_
DATIN
DATIN
LOOP
IN3R_
BACK
_ENA
ENA
ENA
ENA
ENA
DIR
V
V
0
0
DEFAULT
8900h
C000h
00C0h
00C0h
00C0h
00C0h
B001h
004Ch
004Ch
2000h
0000h
4050h
4000h
0008h
0000h
0040h
0040h
1004h
0000h
0100h
0000h
0044h
0044h
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