WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 95

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
R6 (06h)
Clocking 1
R7 (07h)
Clocking 2
REGISTER ADDRESS
14:12
4:1
7:5
12
BIT
8
0
OPCLK_DIV
[2:0]
MCLK_SRC
BCLK_DIV
[3:0]
BCLK_DIR
AIF_TRI
ADC_CLKDIV
[2:0]
LABEL
DEFAULT
0000
000
000
0
0
0
OPCLK Frequency (GPIO function)
000 = SYSCLK
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 5.5
101 = SYSCLK / 6
110 = Reserved
111 = Reserved
Clock Source selection
0 = SYSCLK derived from MCLK
1 = SYSCLK derived from FLL output
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 44
1111 = SYSCLK / 48
BCLK Direction
0 = BCLK is input
1 = BCLK is output
Tri-states ADCDAT and switches ADCLRC,
DACLRC and BCLK to inputs.
0 = ADCDAT is an output; DACLRC and
BCLK may be inputs or outputs; ADCLRC
is input, output or GPIO.
1 = ADCDAT is tri-stated; DACLRC and
BCLK are inputs; ADCLRC is input or
GPIO.
ADC Sample rate divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
DESCRIPTION
PD, August 2008, Rev 4.0
WM8900
95