WM8941GEFL/RV Wolfson Microelectronics, WM8941GEFL/RV Datasheet - Page 58

• Manufacturer Part Number: WM8941GEFL/RV
• Description: Audio CODECs Mono CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8941GEFL/RV

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8941
w
DIGITAL AUDIO INTERFACES
Overall voltage gain (i.e. VBIN to TV input) is calculated as follows:
The audio interface has four pins:
The clock signals BCLK, and FRAME can be outputs when the WM8941 operates as a master, or
inputs when it is a slave (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8941 audio interface may be configured as either master or slave. As a master interface
device the WM8941 generates BCLK and FRAME and thus controls sequencing of the data transfer
on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In
slave mode (MS=0), the WM8941 responds with data to clocks it receives over the digital audio
interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition.
The outputs VBREF and VBOUT are current mirrored transistors with a 5:1 ratio, so that:
i
A reference resistor (187R in above examples) is used for feedback on the video buffer amplifier via
the VBREF pin. The output current from VBOUT will be split between the source termination and
load termination (75R each in above examples).
See applications note WAN0166 for further information.
VBOUT
0
1
VBGAIN
(R40[1])
•
•
•
•
•
•
•
•
= 5 x i
ADCDAT: ADC data output
DACDAT: DAC data input
FRAME: Data alignment clock
BCLK: Bit clock, for synchronisation
Left justified
Right justified
I
DSP mode A / B
2
S
VBREF
5 x (R
10 x (R
.
(SOURCE AND LOAD BOTH
LOADED GAIN FORMULA
TERMINATED WITH 75R)
LOAD
LOAD
|| R
|| R
SOURCE
SOURCE
) / R
) / R
VBREF
VBREF
0dB
+6dB
RSOURCE=75R;
LOADED GAIN
(VREF=187R;
RLOAD=75R)
PP, Rev 3.3, December 2007
+6dB
+12dB
UNLOADED GAIN
RSOURCE=75R;
(VREF=187R;
RLOAD=0)
Pre Production
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