WM8941GEFL/RV Wolfson Microelectronics, WM8941GEFL/RV Datasheet - Page 63

• Manufacturer Part Number: WM8941GEFL/RV
• Description: Audio CODECs Mono CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8941GEFL/RV

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pre Production
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MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
Table 46 Sample Rate Control
The PLL is enabled or disabled by the PLLEN register bit.
Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are
set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.
Table 47 PLLEN Control Bit
The WM8941 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Table 47 shows the PLL and internal clocking arrangement on the WM8941.
R7
Additional
control
R1
Power
Management 1
REGISTER
ADDRESS
•
•
REGISTER
ADDRESS
Generate master clocks for the WM8940 audio functions from another external clock, e.g.
in telecoms applications.
Generate an output clock, on GPIO, for another part of the system (derived from an
existing audio master clock).
3:1
BIT
5
BIT
SR
LABEL
PLLEN
LABEL
000
0
DEFAULT
DEFAULT
PLL enable
0=PLL off
1=PLL on
Approximate sample rate (configures the
coefficients for the internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
DESCRIPTION
PP, Rev 3.3, December 2007
DESCRIPTION
WM8941
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