WM8941GEFL/RV Wolfson Microelectronics, WM8941GEFL/RV Datasheet - Page 65

• Manufacturer Part Number: WM8941GEFL/RV
• Description: Audio CODECs Mono CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8941GEFL/RV

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pre Production
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Table 49 PLL Modes of Operation (Integer N mode)
FRACTIONAL K MODE
EXAMPLE:
The PLL performs best when f
are shown in Table 56.
Table 50 PLL Frequency Examples
If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low
power operation.
The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up
to 1/2
division X, the fractional division K[23:0] and the integer division N[3:0] is:
where 0 < (R – N) < 1 and K is rounded to the nearest whole number.
PLL input clock (f
R should be chosen to ensure 5 < N < 13. There is a fixed divide by 4 in the PLL and a selectable
divider (MCLKDIV[3:0]) after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f
So N[3:0] will be 8h and K[23:0] will be 3126E9h to produce the desired 98.304MHz clock.
(MHz)
19.68
19.68
MCLK
14.4
14.4
19.2
19.2
19.8
19.8
INPUT CLOCK
12
12
13
13
24
24
26
26
27
27
11.2896MHz
12.2880MHz
24
(F
). If these are used then FRAC_EN must be set. The relationship between the required
1
K = 2
R = 98.304 / 12 = 8.192
N = int R = 8
K = int (2
)
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
DESIRED
OUTPUT
(MHz)
24
1
( R – N)
) is 12MHz and the required clock (SYSCLK) is 12.288MHz.
24
x (8.192 – 8)) = 3221225 = 3126E9h
DESIRED PLL
90.3168MHz
98.3040MHz
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
OUTPUT (F
(MHz)
F2
2
is around 90MHz. Its stability peaks at N=8. Some example settings
2
)
PRESCALE
DIVIDE
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
= 4 * 2 * 12.288MHz = 98.304MHz.
REQUIRED (R)
DIVISION
8
8
POSTSCALE
(MCLKDIV)
DIVIDE
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
FRACTIONAL
DIVISION (K)
6.947446
7.561846
6.826667
9.178537
9.990243
9.122909
9.929697
6.947446
7.561846
6.690133
7.281778
0
0
7.5264
7.5264
8.192
6.272
9.408
10.24
8.192
PP, Rev 3.3, December 2007
R
DIVISION (N)
(Hex)
INTEGER
A
7
8
6
7
6
6
9
9
9
9
9
7
8
6
7
6
7
N
8
8
WM8941
BOAC93
45A1CA
D3A06E
F28BD4
3D70A3
2DB492
FD809F
EE009E
F28BD4
86C226
8FD525
1F76F8
86C226
8FD525
3126E9
6872B0
3126E9
482296
(Hex)
K
SDM
0
0
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