WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 113

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pre-Production
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The
WM8903 can be configured using the Control Interface.
R0 (0h)
R1 (1h)
R4 (4h)
R5 (5h)
R6 (6h)
R8 (8h)
R10
(0Ah)
R12 (Ch) Power
R13 (Dh) Power
R14 (Eh) Power
R15 (Fh) Power
R16 (10h) Power
R17 (11h) Power
R18 (12h) Power
R20 (14h) Clock Rates
R21 (15h) Clock Rates
R22 (16h) Clock Rates
R24 (18h) Audio
R25 (19h) Audio
R26
w
REG
SW Reset
and ID
Revision
Number
Bias Control
0
VMID
Control 0
Mic Bias
Control 0
Analogue
DAC 0
Analogue
ADC 0
Management
0
Management
1
Management
2
Management
3
Management
4
Management
5
Management
6
0
1
2
Interface 0
Interface 1
Audio
NAME
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C_TDM
AIFDA
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLK_SYS_RATE[3:0]
C_TDM
_CHAN
DACL_
DATIN
AIFDA
12
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C_TDM
DACR_
DATIN
AIFAD
11
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C_TDM
_CHAN
DAC_BOOST[1:
AIFAD
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0]
CLK_SYS_MOD
LRCLK
_DIR
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SW_RST_DEV_ID1[15:0]
E[1:0]
LOOPB
ACK
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TIE_EN
AIF_BC
LK_INV
VMID_
CL_SR
AIFAD
A
C
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CR_SR
BCLK_
BUFIO
AIFAD
_ENA
DIR
C
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MICDET_THR[1:
VMID_I
O_ENA
DAC_B
CL_SR
AIFDA
IAS_B
OOST
C
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0]
POBCT
CR_SR
AIF_LR
CLK_IN
VMID_SOFT[1:0
DACBIAS_SEL[
AIFDA
RL
C
4
0
0
0
0
0
0
0
0
0
0
0
0
V
1:0]
]
ADC_C
MICSHORT_TH
DACL_
OMP
ENA
AIF_WL[1:0]
3
0
0
0
0
0
0
0
0
0
ISEL[1:0]
R[1:0]
BCLK_DIV[4:0]
SAMPLE_RATE[3:0]
DACVMID_BIAS
DACR_
YS_EN
ADC_C
CLK_S
OMPM
CHIP_REV[3:0]
VMID_RES[1:0] VMID_
PP, Rev 3.1, August 2009
ODE
ENA
0
A
2
0
0
0
0
0
0
0
_SEL[1:0]
INL_EN
GA_EN
GA_EN
DAC_C
START
AS_EN
MICDE
T_ENA
MIXOU
HPL_P
MIXSP
KL_EN
SPKL_
ADCL_
CLK_D
SP_EN
UP_BI
TL_EN
LINEO
UTL_P
OMP
ENA
ENA
AIF_FMT[1:0]
A
A
A
A
A
A
A
1
0
0
BIAS_E
MICBIA
ADC_O
MCLKD
BUF_E
S_ENA
MIXOU
TR_EN
HPR_P
GA_EN
UTR_P
GA_EN
KR_EN
SPKR_
ADCR_
TO_EN
DAC_C
SR128
MIXSP
OMPM
INR_E
LINEO
ODE
ENA
ENA
IV2
NA
NA
NA
A
A
A
A
A
0
0
WM8903
DEFAULT
0C08h
8903h
0002h
0018h
0000h
0000h
0001h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0400h
0000h
0050h
0002h
0008h
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