WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 114

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
(1Ah)
R27
(1Bh)
R30
(1Eh)
R31 (1Fh) DAC Digital
R32 (20h) DAC Digital
R33 (21h) DAC Digital
R36 (24h) ADC Digital
R37 (25h) ADC Digital
R38 (26h) ADC Digital
R40 (28h) DRC 0
R41 (29h) DRC 1
R42
(2Ah)
R43
(2Bh)
R44
(2Ch)
R45
(2Dh)
R46
(2Eh)
R47 (2Fh) Analogue
R50 (32h) Analogue
R51 (33h) Analogue
R52 (34h) Analogue
R53 (35h) Analogue
R54 (36h) Analogue
R55 (37h) Analogue
w
REG
Interface 2
Audio
Interface 3
DAC Digital
Volume Left
Volume
Right
0
1
Volume Left
Volume
Right
0
DRC 2
DRC 3
Analogue
Left Input 0
Analogue
Right Input 0
Analogue
Left Input 1
Right Input 1
Left Mix 0
Right Mix 0
Spk Mix Left
0
Spk Mix Left
1
Spk Mix
Right 0
Spk Mix
NAME
DRC_E
NA
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC_ATTACK_RATE[3:0]
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAC_M
DRC_THRESH_
ONO
12
0
0
0
0
0
0
0
HYST[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
DAC_S
B_FILT
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC_DECAY_RATE[3:0]
ADCL_DAC_SVOL[3:0]
DAC_M
UTERA
TE
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC_STARTUP_GAIN[4:0]
DAC_M
UTEM
ODE
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC_THRESH_COMP[5:0]
DACVU
DACVU
ADCVU
ADCVU
8
0
0
0
0
0
0
0
0
0
0
0
0
0
DRC_THRESH_
RINMU
LINMU
TE
TE
7
0
0
0
0
0
0
0
0
0
0
0
QR[1:0]
ADCR_DAC_SVOL[3:0]
ADC_HPF_CUT[
M_ENA
M_ENA
INR_C
INL_C
LRCLK_RATE[10:0]
6
0
0
0
0
0
0
0
0
0
0
1:0]
R_IP_SEL_N[1:0
DRC_F
DRC_RATE_QR
DRC_R0_SLOPE_COMP
L_IP_SEL_N[1:0
F_DEL
AY
5
0
0
0
0
0
0
0
0
0
[1:0]
]
]
ADC_H
DACR_VOL[7:0]
ADCR_VOL[7:0]
PF_EN
DACL_VOL[7:0]
ADCL_VOL[7:0]
[2:0]
4
0
A
0
0
0
0
0
0
0
ADC_TO_DACL[
DAC_M
R_IP_SEL_P[1:0
XOUTR
DRC_S
H_ENA
L_IP_SEL_P[1:0
XOUTL
XSPKR
DRC_MINGAIN[
DACL_
DACL_
DACL_
XSPKL
DACL_
MIXSP
KL_VO
DACL_
DACL_
MIXSP
MOOT
TO_MI
TO_MI
TO_MI
TO_MI
DRC_AMP_COMP[4:0]
UTE
3
0
L
RIN_VOL[4:0]
LIN_VOL[4:0]
1:0]
1:0]
]
]
DRC_Q
XOUTR
XSPKR
R_ENA
DRC_R1_SLOPE_COMP
DACR_
XOUTL
DACR_
DACR_
XSPKL
DACR_
KL_VO
DACR_
DACR_
TO_MI
TO_MI
TO_MI
MIXSP
TO_MI
MIXSP
DEEMPH[1:0] DAC_O
PP, Rev 3.1, August 2009
2
0
L
ADC_TO_DACR
DRC_A
BYPAS
BYPAS
BYPAS
BYPAS
BYPAS
BYPAS
ADCL_
NTICLI
P_ENA
DRC_MAXGAIN
SL_TO
SL_TO
SL_TO
XSPKL
SL_TO
DATIN
_MIXO
_MIXO
_MIXS
SL_MI
_MIXS
SL_MI
_VOL
L_MODE[1:0]
R_MODE[1:0]
UTR
PKR
[2:0]
UTL
PKL
V
1
[1:0]
[1:0]
ADCR_
DRC_H
YST_E
BYPAS
SR_TO
BYPAS
SR_TO
BYPAS
SR_TO
BYPAS
XSPKL
BYPAS
SR_TO
BYPAS
_MIXO
_MIXO
_MIXS
SR_MI
_MIXS
SR_MI
DATIN
_VOL
UTR
PKR
Pre-Production
UTL
PKL
SR
NA
V
0
DEFAULT
00C0h
00C0h
00C0h
00C0h
0022h
0000h
0000h
0000h
3241h
0020h
0000h
0085h
0085h
0044h
0044h
0008h
0004h
0000h
0000h
0000h
0000h
09Afh
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