WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 40

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
DYNAMIC RANGE CONTROL (DRC)
w
ADC OVERSAMPLING RATIO (OSR)
The ADC oversampling rate is programmable to allow power consumption versus audio performance
trade-offs. The default oversampling rate is high for best performance; using the lower OSR setting
reduces ADC power consumption.
Table 13 ADC Oversampling Ratio
Note that the Low Power (64 x fs) oversampling option is not supported when CLK_SYS_MODE=10
(see “Clocking and Sample Rates”, Table 61).
The dynamic range controller (DRC) is a circuit which can be enabled in the digital data path of the
ADC. Its function is to adjust the signal gain in conditions where the input amplitude is unknown or
varies over a wide range, e.g. when recording from microphones built into a handheld system. The
DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anti-clip’
and ‘quick release’ features for handling transients in order to improve intelligibility in the presence of
loud impulsive noises.
The DRC is enabled as shown in Table 14.
Table 14 DRC Enable
COMPRESSION/LIMITING CAPABILITIES
The DRC supports two different compression regions, specified by R0 and R1, separated by a “knee”
at input amplitude T. For signals above the knee, the compression slope R0 applies; for signals
below the knee, the compression slope R1 applies.
The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is near-
constant) is illustrated in Figure 30.
R10 (0Ah)
Analogue ADC
0
R40 (28h)
DRC 0
REGISTER
REGISTER
ADDRESS
ADDRESS
BIT
BIT
15
0
ADC_OSR128
DRC_ENA
LABEL
LABEL
DEFAULT
DEFAULT
1
0
ADC Oversampling Ratio
0 = Low Power (64 x fs)
1 = High Performance (128 x fs)
Note that the Low Power options is
not supported when
CLK_SYS_MODE=10
DRC enable
1 = enabled
0 = disabled
PP, Rev 3.1, August 2009
DESCRIPTION
DESCRIPTION
Pre-Production
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