WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 73

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pre-Production
DC SERVO
w
For example, with MCLKDIV2=0
256fs gives a charge pump clock division ratio of 12, hence
128fs gives a charge pump clock division ratio of 6, hence
CHARGE PUMP REGISTERS
The Charge Pump control fields are described in Table 48.
Table 48 Charge Pump Control
The WM8903 provides a DC servo circuit on the headphone and line outputs in order to remove DC
offset from these ground-referenced outputs. When enabled, the DC servo ensures that the DC level
of these outputs remains within 1.5mV of ground. Removal of the DC offset is important because any
deviation from GND at the output pin will cause current to flow through the load under quiescent
conditions, resulting in increased power consumption. Additionally, the presence of DC offsets can
result in audible pops and clicks at power up and power down.
The recommended usage of the DC Servo is initialised by running the default Start-Up sequence as
described in the “Control Write Sequencer” section. The default Start-Up sequence selects
START_STOP servo mode, which causes a one-off correction to be performed, after which the
measured DC offset is then maintained on the headphone and line outputs.
If a different usage is required, e.g. if one or more of the outputs is not in use, or if periodic DC offset
correction is required, then the default Start-Up sequence may be modified according to specific
requirements. The relevant control fields are defined in Table 49 .
If DC offset correction is not required on any output, then DCS_MASTER_ENA should be set to 0.
Setting this field to 0 before running the Start-Up sequence will disable the DC Servo on all outputs.
If DC offset correction is only required on selected channels, then DCS_ENA should be set
accordingly. Setting this field to 1111b enables the DC Servo on all outputs. Setting any bit to 0
disables the DC Servo on the corresponding output. Disabling the DC Servo on unused outputs
reduces power consumption in the device. To modify this within the Start-Up sequence, the data in
WSEQ Address 23 and WSEQ Address 24 should be updated (see “Control Write Sequencer”)
before running the sequence.
R98 (62h)
Charge Pump
0
R104 (68h)
Class W 0
REGISTER
ADDRESS
•
•
•
•
MCLK=12.288MHz gives a charge pump frequency of 1.024MHz at full output power.
MCLK=11.2896MHz gives a charge pump frequency of 940.8kHz at full output power.
MCLK=6.144MHz gives a charge pump frequency of 1.024MHz at full output power.
MCLK=5.6448MHz gives a charge pump frequency of 940.8kHz at full output power
BIT
0
0
CP_ENA
CP_DYN_PWR
LABEL
DEFAULT
0
0
Enable charge-pump digits
0 = disable
1 = enable
Enable dynamic charge pump
power control
0 = charge pump controlled by
volume register settings
1 = charge pump controlled by real-
time audio level
PP, Rev 3.1, August 2009
DESCRIPTION
WM8903
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