WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 82

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
w
Figure 46 TDM with Third Audio Device as Master
The WM8903 supports TDM in master and slave modes, for both incoming and outgoing audio data,
in all data formats and word lengths. When TDM is enabled, two time slots (Slot 0 and Slot 1) are
available on the ADCDAT and/or DACDAT pins. The control bits for TDM are shown in Table 54.
Table 54 TDM Control
When TDM is enabled, the ADCDAT pin is tri-stated immediately before and immediately after data
transmission, to allow another audio device to drive this signal line for the remainder of the sample
period. It is important that two devices do not attempt to drive the data pin simultaneously, as this
could result in a short circuit (see “Signal Timing Requirements” for details of the ADCDAT output
relative to BCLK signal). The transmission times of two devices can be prevented from overlapping
by providing additional, unused BCLK cycles. For example, the audio interface could run at 32 BCLK
cycles per data sample even though the WM8903 word length is only 24-bit. This creates an 8-bit
gap between transmissions. When using such a scheme, it is recommended to add pull-down
resistors to the DACDAT and ADCDAT lines, as shown in Figure 45, and Figure 46.
Note: The WM8903 is a 24-bit device. In 32-bit mode (AIF_WL=11), the 8 LSBs are ignored on the
receiving side and not driven on the transmitting side.
R25 (19h)
Audio
Interface 1
REGISTER
ADDRESS
WM8903
device
audio
Third
ADCDAT
DACDAT
BCLK
ADCDAT
DACDAT
BCLK
LRC
LRC
BIT
13
12
11
10
AIFDAC_TDM
AIFDAC_TDM_
CHAN
AIFADC_TDM
AIFADC_TDM_
CHAN
LABEL
Processor
DEFAULT
0
0
0
0
DAC TDM Enable
0 = Normal DACDAT operation
1 = TDM enabled on DACDAT
DACDAT TDM Channel Select
0 = DACDAT data input on slot 0
1 = DACDAT data input on slot 1
ADC TDM Enable
0 = Normal ADCDAT operation
1 = TDM enabled on ADCDAT
ADCDAT TDM Channel Select
0 = ADCDAT outputs data on slot 0
1 = ADCDAT output data on slot 1
PP, Rev 3.1, August 2009
DESCRIPTION
Pre-Production
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