WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 87

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pre-Production
CLOCKING AND SAMPLE RATES
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The WM8903 supports a wide range of standard audio sample rates from 8kHz to 96kHz. When the
DAC and ADC are both enabled, they operate at the same sample rate, f
Note that the 88.2kHz and 96kHz sample rate settings are not valid for Digital Microphone operation,
or ADC in USB mode.
CLOCKING ARCHITECTURE
All internal clocks are derived from MCLK, as shown in Figure 54. Note that BCLK and LRC are
described in the “Digital Audio Interface” section.
Figure 54 WM8903 Clocking Overview
The system clock is enabled using the CLK_SYS_ENA register bit, which should be enabled for
normal operation with MCLK applied.
The DSP clocking is enabled by CLK_DSP_ENA. For normal operation, CLK_DSP_ENA must be
set. Note that the default Start-Up sequence (see “Control Write Sequencer”) causes the
CLK_DSP_ENA bit to be set.
The Zero-Cross feature associated with the Output PGA volume updates includes a timeout option to
ensure the volume update occurs even if a zero cross is not detected. To enable this timeout, the
TO_ENA bit must be set.
The internal clock CLK_SYS is derived from MCLK as controlled by MCLKDIV2 (see Table 61). The
SAMPLE_RATE field should be set according to the desired Sample Rate (fs). Given the ratio of
CLK_SYS to fs, the control fields CLK_SYS_RATE and CLK_SYS_MODE should be set in
accordance with Table 62. When these fields are set correctly, the Sample Rate Decoder circuit
automatically determines the clocking configuration for all other circuits within the WM8903.
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PP, Rev 3.1, August 2009
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WM8903
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