WM9713LGEFL/RV Wolfson Microelectronics, WM9713LGEFL/RV Datasheet

Audio CODECs Stereo AC'97 CODEC T/P Interface

WM9713LGEFL/RV

Manufacturer Part Number
WM9713LGEFL/RV
Description
Audio CODECs Stereo AC'97 CODEC T/P Interface
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM9713LGEFL/RV

Number Of Adc Inputs
1
Number Of Dac Outputs
1
Conversion Rate
8 KSPs
Interface Type
AC97
Resolution
12 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-48
Minimum Operating Temperature
- 25 C
Number Of Channels
1 ADC, 1 DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
WM9713LGEFL/RV
Manufacturer:
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WM9713LGEFL/RV
Manufacturer:
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Quantity:
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DESCRIPTION
The WM9713L is a highly integrated input/output device
designed for mobile computing and communications.
The chip is architected for dual CODEC operation, supporting
Hi-Fi stereo Codec functions via the AC link interface, and
additionally supporting voice Codec functions via a PCM type
Synchronous Serial Port (SSP). A third, auxiliary DAC is
provided which may be used to support generation of
supervisory tones, or ring-tones at different sample rates to the
main codec.
The device can connect directly to a 4-wire or 5-wire touch-
panel, mono or stereo microphones, stereo headphones and a
stereo speaker, reducing total component count in the system.
Cap-less connections to the headphones, speakers, and
earpiece may be used, saving cost and board area. Additionally,
multiple analog input and output pins are provided for seamless
integration with analog connected wireless communication
devices.
All device functions are accessed and controlled through a
single AC-Link interface compliant with the AC’97 standard.
The 24.576MHz masterclock can be input directly or generated
internally from a 13MHz (or other frequency) clock by an on-chip
PLL.
2.048MHz to 78.6MHz.
The WM9713L operates at supply voltages from 1.8V to 3.6V.
Each section of the chip can be powered down under software
control to save power. The device is available in a small
leadless 7x7mm QFN package, ideal for use in hand-held
portable systems.
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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The PLL supports a wide range of input clock from
AC’97 Audio + Touchpanel CODEC
at
http://www.wolfsonmicro.com/enews/
FEATURES
• AC’97 Rev 2.2 compatible stereo codec
• On-chip 45mW headphone driver
• On-chip 400mW mono or stereo speaker drivers
• Stereo, mono or differential microphone input
• Auxiliary mono DAC (ring tone or DC level generation)
• Seamless interface to wireless chipset
• Resistive touchpanel interface
• Additional PCM/I
• PLL derived audio clocks.
• Supports input clock ranging from 2.048MHz to 78.6MHz
• 1.8V to 3.6V supplies (digital down to 1.62V, speaker up to
• 7x7mm 48-lead QFN package
APPLICATIONS
• Smartphones
• Personal Digital Assistants (PDA)
• Handheld and Tablet Computers
- DAC SNR 94dB, THD –85dB
- ADC SNR 87dB, THD –86dB
- Variable Rate Audio, supports all WinCE sample rates
- Tone Control, Bass Boost and 3D Enhancement
- Automatic Level Control (ALC)
- Mic insert and mic button press detection
- Supports 4-wire and 5-wire panels
- 12-bit resolution, INL ±2 LSBs (<0.5 pixels)
- X, Y and touch-pressure (Z) measurement
- Pen-down detection supported in Sleep Mode
4.2V)
Copyright ©2008 Wolfson Microelectronics plc
2
S interface to support voice CODEC
Pre-Production, September 2008, Rev 3.2
WM9713L

Related parts for WM9713LGEFL/RV

WM9713LGEFL/RV Summary of contents

Page 1

... QFN package APPLICATIONS • Smartphones • Personal Digital Assistants (PDA) • Handheld and Tablet Computers http://www.wolfsonmicro.com/enews/ WM9713L 2 S interface to support voice CODEC Pre-Production, September 2008, Rev 3.2 Copyright ©2008 Wolfson Microelectronics plc ...

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WM9713L DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................7 ELECTRICAL CHARACTERISTICS ......................................................................8 AUDIO OUTPUTS.......................................................................................................... 8 AUDIO INPUTS.............................................................................................................. 9 AUXILIARY MONO DAC ...

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Pre-Production DIFFERENTIAL MONO INPUT .................................................................................... 52 AUDIO MIXERS....................................................................................................53 MIXER OVERVIEW ..................................................................................................... 53 HEADPHONE MIXERS ................................................................................................ 53 SPEAKER MIXER ........................................................................................................ 53 MONO MIXER.............................................................................................................. 54 MIXER OUTPUT INVERTERS..................................................................................... 54 ANALOGUE AUDIO OUTPUTS ...........................................................................55 HEADPHONE OUTPUTS – HPL AND HPR................................................................. 55 MONO OUTPUT ...

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... WM9713L PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE DEVICE RANGE o WM9713LGEFL/V -25 to +85 o WM9713LGEFL/RV -25 to +85 Note: Reel quantity = 2,200 w MOISTURE SENSITIVITY PACKAGE 48-lead QFN C (Pb-free) 48-lead QFN C (Pb-free, tape and reel) Pre-Production PEAK SOLDERING LEVEL TEMPERATURE o MSL3 260 C o MSL3 260 C PP Rev 3.2 September 2008 ...

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Pre-Production PIN DESCRIPTION PIN NAME 1 DBVDD 2 MCLKA 3 MCLKB / GPIO6 / (ADA / MASK) 4 DGND1 5 SDATAOUT 6 BITCLK 7 DGND2 8 SDATAIN 9 DCVDD 10 SYNC 11 RESETB / GPIO7 / (PENDOWN) 12 WIPER / ...

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WM9713L PIN NAME 44 GPIO1 / PCMCLK 45 GPIO2 / IRQ 46 GPIO3 / PENDOWN / PCMFS 47 GPIO4 / ADA / MASK / PCMDAC 48 GPIO5 / S/PDIF / PCMADC 49 GND_PADDLE Notes recommended that the ...

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Pre-Production RECOMMENDED OPERATING CONDITIONS PARAMETER Digital input/output buffer supply range Digital core supply range Analogue supply range AVDD, HPVDD, Speaker supply range Digital ground DGND1, DGND2 Analogue ground AGND, HPGND, SPKGND, TPGND Difference AGND to DGND Note: 1. AGND is ...

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WM9713L ELECTRICAL CHARACTERISTICS AUDIO OUTPUTS Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD=HPVDD=SPKVDD =3.3V, T otherwise stated. PARAMETER SYMBOL DAC to Line-Out (HPL/R, SPKL/R or MONO with 10kΩ / 50pF load) Full-scale output (0dBFS) Signal to Noise Ratio (A-weighted) Total Harmonic ...

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Pre-Production AUDIO INPUTS Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, T PARAMETER LINEL/R, MIC1/2A/2B, MONOIN and PCBEEP pins Full Scale Input Signal Level (0dBFS) Input Resistance Input Capacitance Line input to ADC (LINEL, LINER, MONOIN) Signal to Noise ...

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WM9713L TOUCHPANEL AND AUXILIARY ADC Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, AVDD = 3.3V, T PARAMETER Input Pins X+, X-, Y+, Y-, WIPER/AUX4, COMP1/AUX1, COMP2/AUX2 Input Voltage Input leakage current ADC Resolution Differential Non-Linearity Error DNL Integral Non-Linearity ...

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Pre-Production DIGITAL INTERFACE CHARACTERISTICS Test Conditions DBVDD = 3.3V, DCVDD = 3.3V PARAMETER Digital Logic Levels (all digital input or output pins) – CMOS Levels Input HIGH level V Input LOW level V Output HIGH level V Output ...

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WM9713L SIGNAL TIMING REQUIREMENTS AC97 INTERFACE TIMING CLOCK SPECIFICATIONS BITCLK Figure 1 Clock Specifications (50pF External Load) Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V -25°C to +85°C, unless otherwise stated. BITCLK frequency ...

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Pre-Production DATA SETUP AND HOLD Figure 2 Data Setup and Hold (50pF External Load) Note: Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9713L. Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 ...

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WM9713L SIGNAL RISE AND FALL TIMES BITCLK SDATAIN SDATAOUT Figure 3 Signal Rise and Fall Times (50pF External Load) Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V -25°C to +85°C, unless otherwise stated. ...

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Pre-Production COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS) Figure 5 Cold Reset Timing Note: For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active low period otherwise the device may enter test mode. See AC'97 specification or ...

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WM9713L PCM AUDIO INTERFACE TIMING – SLAVE MODE Figure 7 Digital Audio Data Timing – Slave Mode Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V -25°C to +85°C, unless otherwise stated. PARAMETER Audio ...

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Pre-Production PCM AUDIO INTERFACE TIMING – MASTER MODE Figure 8 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V -25°C to +85°C, unless otherwise ...

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WM9713L DEVICE DESCRIPTION INTRODUCTION The WM9713L is a largely pin compatible upgrade to WM9712, with a PCM voice codec added. This codec is interfaced via a PCM type audio interface which makes use of GPIO pins for connection ...

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Pre-Production AUDIO PATHS OVERVIEW (Loopback) AC'97 Link ADC Left 00000 = +12dB 11111 = -34.5dB LINEL 00000 = +12dB 11111 = -34.5dB MONOIN PCBEEP 00000 = +12dB 11111 = -34.5dB (Loopback) AC'97 Link ADC Right 00000 = +12dB 11111 = ...

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WM9713L CLOCK GENERATION WM9713L supports clocking from 2 separate sources, which can be selected via the AC’97 interface: • External clock input MCLKA • External clock input MCLKB The source clock is divided to appropriate frequencies in order to run ...

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Pre-Production Figure 10 Clocking Architecture for WM9713L INTERNAL CLOCK FREQUENCIES The internal clock frequencies are defined as follows (refer to Figure 10): • AC97 CLK – nominally 24.576MHz, used to generate AC97 BITCLK at 12.288MHz • HIFI CLK – for ...

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WM9713L Clock mode and division ratios are controlled by register 44h as shown in Table 3. REGISTER ADDRESS 44h Table 3 Clock Muxing and Division Control w BIT LABEL DEFAULT 14:12 S [6:4] 000 (div 1) EXT 11:8 S [3:0] ...

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Pre-Production PLL MODE The PLL operation is controlled by register 46h (see Table 4) and has two modes of operation: • • The PLL has been optimized for nominal input clock (PLL_IN) frequencies in the range 8.192MHz – 19.661MHz (LF=0) ...

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WM9713L INTEGER N MODE The nominal output frequency of the PLL (PLL_OUT) is 98.304MHz which is divided achieve a nominal system clock of 24.576MHz. The integer division ratio (N) is determined by: F the range 5 to ...

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Pre-Production PLL REGISTER PAGE ADDRESS MAPPING The clock division control bits S register 46h using a sub-page address system. The 3 bit pager address allows 8 blocks of 4 bit data words to be accessed whilst the register address is ...

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WM9713L DIGITAL INTERFACES The WM9713L has two interfaces, a data and control AC’97 interface and a data only PCM interface. The AC’97 interface is available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK and RESETB) and is the sole control interface ...

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Pre-Production PCM INTERFACE OPERATION WM9713L can implement a PCM voice codec function using the dedicated VXDAC and either one or both of the existing hi-fi ADC’s. In PCM codec mode, VXDAC input and ADC output are interfaced via a PCM ...

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WM9713L The PCM Interface may be configured for Mono mode, where only one channel of ADC data is output. In this mode the interface should be configured for DSP mode. A short or long frame sync is supported and the ...

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Pre-Production In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of PCMCLK (selectable by FSP) following a rising edge of PCMFS. Right channel data immediately follows left channel ...

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WM9713L In Left Justified mode, the MSB is available on the first rising edge of PCMCLK following a PCMFS transition. The other bits up to the LSB are then transmitted in order. Depending on word length, PCMCLK frequency and sample ...

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Pre-Production CONTROL The register bits controlling PCM audio format, word length and operating modes are summarised below. CTRL must be set to override the normal use of the PCM interface pins as GPIOs, MODE must be set to specify master/slave ...

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WM9713L AUDIO ADCS STEREO ADC The WM9713L has a stereo sigma-delta ADC to digitize audio signals. The ADC achieves high quality audio recording at low power consumption. The ADC sample rate can be controlled by writing to a control register ...

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Pre-Production RECORD SELECTOR The record selector determines which input signals are routed into the audio ADC. The left and right channels can be selected independently. This is useful for recording a phone call: one channel can be used for the ...

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WM9713L RECORD GAIN The amplitude of the signal that enters the audio ADC is controlled by the Record PGA (Programmable Gain Amplifier). The PGA gain can be programmed either by writing to the Record Gain register the Automatic ...

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Pre-Production REGISTER ADDRESS 14h Record Routing Table 13 Record PGA Routing Control w BIT LABEL DEFAULT 15:14 R2H 11 (mute) Record Mux to Headphone Mixer Path Control 00 = stereo 01 = left ADC only 10 = right ADC only ...

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WM9713L AUTOMATIC LEVEL CONTROL The WM9713L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at ...

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Pre-Production When operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ...

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WM9713L MAXIMUM GAIN The MAXGAIN register sets the maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled. PEAK LIMITER To ...

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Pre-Production AUDIO DACS STEREO DAC The WM9713L has a stereo sigma-delta DAC that achieves high quality audio playback at low power consumption. Digital tone control, adaptive bass boost and 3-D enhancement functions operate on the digital audio data before it ...

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WM9713L TONE CONTROL / BASS BOOST The WM9713L provides separate controls for bass and treble with programmable gains and filter characteristics. This function operates on digital audio data before it is passed to the audio DACs. Bass control can take ...

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Pre-Production 3D STEREO ENHANCEMENT The 3D stereo enhancement function artificially increases the separation between the left and right channels by amplifying the (L-R) difference signal in the frequency range where the human ear is sensitive to directionality. The programmable 3D ...

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WM9713L VOICE DAC VXDAC is a 16-bit mono DAC intended for playback of Rx voice signals input via the PCM interface. Performance has been optimised for operating at 8ks/s or 16ks/s. The VXDAC will function at other sample rates up ...

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Pre-Production REGISTER ADDRESS 3Ch Powerdown (1) 64h AUXDAC Input Control 1Ah AUXDAC Output Control Table 20 AUXDAC Control w BIT LABEL DEFAULT 11 AUXDAC 0 AUXDAC Disable Control 1 = Disabled 0 = Enabled 15 XSLE 0 AUXDAC Input Select ...

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WM9713L VARIABLE RATE AUDIO / SAMPLE RATE CONVERSION By using an AC’97 Rev2.2 compliant audio interface, the WM9713L can record and playback at all commonly used audio sample rates, and offer full split-rate support (i.e. the DAC, ADC and AUXDAC ...

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Pre-Production AUDIO INPUTS The following sections give an overview of the analogue audio input pins and their function. For more information on recommended external components, please refer to the “Applications Information” section. LINE INPUT The LINEL and LINER inputs are ...

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WM9713L MICROPHONE INPUT MICROPHONE PRE-AMPS There are two microphone pre-amplifiers, MPA and MPB, which can be configured in a variety of ways to accommodate selectable differential microphone inputs or 2 differential microphone inputs operating simultaneously for stereo ...

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Pre-Production SINGLE MIC OPERATION Up to three microphones can be connected in a single-ended configuration. Any one of the three MICs can be selected as the input to MPA using MPASEL[1:0] (Register 22h, bits 13:12). Only the microphone on MIC2B ...

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WM9713L MICROPHONE BIASING CIRCUIT The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can ...

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Pre-Production MICBIAS CURRENT DETECT The WM9713L includes a microphone bias current detect circuit with programmable thresholds for the microphone bias current, above which an interrupt will be triggered. There are two separate interrupt bits, MICDET to e.g. distinguish between one ...

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WM9713L MICROPHONE PGAS The microphone pre-amps MPA and MPB drive into two microphone PGAs whose gain is controlled by register 0Eh. The PGA signals can be routed into the headphone mixers and the mono mixer, but not the speaker mixer ...

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Pre-Production MONOIN INPUT Pin 20 (MONOIN mono input designed to connect to the receive path of a telephony device. The pin connects directly to the record selector for phone call recording (Note: to record both sides of a ...

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WM9713L PCBEEP INPUT Pin 19 (PCBEEP mono, line level input intended for externally generated signal or warning tones routed directly to the record selector and all three output mixers, without an input amplifier. The signal gain ...

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Pre-Production AUDIO MIXERS MIXER OVERVIEW The WM9713L has four separate low-power audio mixers to cover all audio functions required by smartphones, PDAs and handheld computers. These mixers are used to drive the audio outputs HPL, HPR, MONO, SPKL, SPKR, OUT3 ...

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WM9713L MONO MIXER The mono mixer drives the MONO pin. The following signals can be mixed into MONO: • • • • • • • typical smartphone application, the MONO signal is a mix of the amplified microphone ...

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Pre-Production ANALOGUE AUDIO OUTPUTS The following sections give an overview of the analogue audio output pins. The WM9713L has three outputs capable of driving loads down to 16Ω (headphone / line drivers) – HPL, HPR and MONO - and four ...

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WM9713L REGISTER ADDRESS 04h Headphone Volume Table 33 HPL / HPR PGA Control MONO OUTPUT The MONO output (pin 31) is designed to drive a 16Ω headphone load and can also be used as a line output. The available input ...

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Pre-Production REGISTER ADDRESS 08h MONO Vol Table 35 Mono PGA Control SPEAKER OUTPUTS – SPKL AND SPKR The SPKL and SPKR (pins 35 and 36) are designed to drive a loudspeaker load down to 8Ω and can also be used ...

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WM9713L REGISTER ADDRESS 02h Speaker Volume Table 37 SPKL / SPKR PGA Control Note: 1. For BTL speaker drive recommended that both PGAs have the same gain setting. AUXILIARY OUTPUTS – OUT3 AND OUT4 The OUT3 and OUT4 ...

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Pre-Production When not in use OUT3 and OUT4 can be powered down using the Powerdown register bits OUT3 and OUT4 (register 3Eh, bits [11:12]). To minimise pops and clicks when the PGA is powered down / recommended ...

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WM9713L JACK INSERTION AND AUTO-SWITCHING In a phone application, a BTL ear speaker may be connected across MONO and HPL, a stereo headphone on HPL and HPR and stereo speakers on SPKL, SPKR, OUT3 and OUT4 (see Figure 23). Typically, ...

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Pre-Production speaker driver are disabled and internally connected to VREF on jack insert. This maintains VREF at those outputs and helps prevent pops when the outputs are enabled. Finally if the user wishes to DC couple the headphone outputs the ...

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WM9713L MODE DESCRIPTION Jack Insert Detection Disabled Jack Insert Detection Enabled. Headphone plugged in. No Ear Speaker Selected. AC Coupled Headphone Selected Jack Insert Detection Enabled. Headphone plugged ...

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Pre-Production DIGITAL AUDIO (S/PDIF) OUTPUT The WM9713L supports the S/PDIF standard. Pins 48 & 12 can be used to output the S/PDIF data. Note that pins 48 & 12 can also be used as GPIO pins. The GE5 & GE8 ...

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WM9713L REGISTER ADDRESS 2Ah Extended Audio 3Ah S/PDIF Control Register 5Ch Additional Function Control Table 45 S/PDIF Output Control w BIT LABEL DEFAULT 10 SPCV 0 S/PDIF Validity Bit (Read Only Valid 0 = Not valid 5:4 SPSA ...

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Pre-Production TOUCHPANEL INTERFACE The WM9713L includes a touchpanel driver and digitiser circuit for use with 4-wire or 5-wire resistive touchpanels. The following functions are implemented: X co-ordinate measurement Y co-ordinate measurement Pen down detection, with programmable sensitivity Touch pressure measurement ...

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WM9713L PRINCIPLE OF OPERATION - FOUR-WIRE TOUCHPANEL Four-wire touchpanels are connected to the WM9713L as follows: • • • • The principle of operation is illustrated below (Note: the illustrations assume that the top plate is used for X and ...

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Pre-Production Figure 27 Pen Down Detection on 4-wire Touchpanel Pen down detection uses a zero power comparator (effectively a CMOS logic gate) with an internal, programmable pull-up resistor R touchpanel less sensitive to touch, while lowering R When the touchpanel ...

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WM9713L PRINCIPLE OF OPERATION - FIVE-WIRE TOUCHPANEL Five-wire touchpanels are connected to the WM9713L as follows: Top sheet contact = WIPER/AUX4 (pin 12) Top left corner of bottom sheet = TL (pin 16) Top right corner of bottom sheet = ...

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Pre-Production Y co-ordinate measurements are similar to Y co-ordinate measurements. However, the voltage gradient on the bottom plate is in the Y direction instead of the X direction. This is achieved by grounding the bottom left and bottom right corners ...

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WM9713L CONTROLLING THE TOUCHPANEL DIGITISER All touchpanel functions are accessed and controlled through the AC-Link interface. PHYSICAL CHARACTERISTICS The physical characteristics of the touchpanel interface are controlled through register 78h, as shown below. REGISTER ADDRESS 78h Table 46 Touchpanel Digitiser ...

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Pre-Production INITIATION OF MEASUREMENTS The WM9713L touchpanel interface supports both polling routines and DMA (direct memory access) to control the flow of data from the touchpanel ADC to the host CPU polling routine, the CPU starts each measurement ...

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WM9713L MEASUREMENT TYPES The ADCSEL control bits determine which type of measurement is performed (see below). REGISTER ADDRESS 74h Table 49 Touchpanel Digitiser Control (Measurement Types) When COO is ‘0’, the WM9713L performs a single measurement – either in polling ...

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Pre-Production CONVERSION RATE As stated previously the conversion rate is specified by the CR bits (reg 76h). CR may be set to 93.75Hz (every 512 AC-Link Frames), 120Hz (every 400 AC-Link Frames), 153.75Hz (every 312 AC-Link frames) or 187.5Hz (every ...

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WM9713L When operating in co-ordinate mode (COO=1) there will be 3 results to read back from each set of measurements – namely X,Y and the third additional measurement. After the co-ordinate set has finished the X result will be present ...

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Pre-Production REGISTER ADDRESS 76h Table 51 Returning Touchpanel Data Through an AC-Link Time Slot w BIT LABEL DEFAULT 3 SLEN 0 Slot Readback Enable Control 0 = Disabled (readback through register map only Enabled (readback slot selected by ...

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WM9713L TOUCHPANEL SETTLING TIME For accurate touchpanel measurements, some settling time may be required between the switch matrix applying a voltage across the touchpanel plate and the ADC sampling the signal. This time delay function is built into the WM9713L ...

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Pre-Production NUMBERS OF ADCSEL[1:7] BITS SET 5,6,7 5,6,7 5,6,7 5,6,7 1 (if COO=1) 1 (if COO=1) 1 (if COO=1) 1 (if COO=1) 2,3,4,5,6,7 (if COO=1) 2,3,4,5,6,7 (if COO=1) 2,3,4,5,6,7,8 (if COO=1) 2,3,4,5,6,7,8 ...

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WM9713L MASK INPUT CONTROL Sources of glitch noise, such as the signals driving an LCD display, may feed through to the touchscreen plates and affect measurement accuracy. In order to minimise this effect, a signal may be applied to MASK ...

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Pre-Production ADDITIONAL FEATURES AUXILIARY ADC INPUTS The ADC used for touchpanel digitisation can also be used for the sole purpose of auxiliary measurements, provided that it is enabled (register 78h, PRP = 11). The WM9713L has three pins that can ...

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WM9713L BATTERY ALARM AND ANALOGUE COMPARATORS The battery alarm function differs from battery measurement in that it does not actually measure the battery voltage. Battery alarm only indicates “OK”, “Low” or “Dead”. The advantage of the battery alarm function is ...

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Pre-Production The WM9713L has two on-chip comparators that can be used to implement a battery alarm function, or other functions such as a window comparator. Each comparator has one of its inputs tied to COMP1 (pin 29) or COMP2 (pin ...

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WM9713L COMP2 DELAY FUNCTION COMP2 has an optional delay function for use when the input signal is noisy. When COMP2 triggers and the delay is enabled (i.e. COMP2DEL is non-zero), then GPIO bit 14 does not change state immediately, and ...

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Pre-Production GPIO AND INTERRUPT CONTROL The WM9713L has eight GPIO pins that operate as defined in the AC’97 Revision 2.2 specification. Each GPIO pin can be set input output, and has corresponding bits in ...

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WM9713L Figure 35 GPIO Logic GPIO SLOT TYPE 12 BIT BIT 1 5 GPIO Pin 2 6 GPIO Pin 3 7 GPIO Pin 4 8 GPIO Pin 5 9 GPIO Pin 6 10 GPIO Pin 7 11 GPIO Pin 8 ...

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Pre-Production Note: GPIO7 (Pin 11) has an independent RESETB function. This must be disabled using RSTDIS (Register 5Ah, bit 8) before using Pin GPIO / PENDOWN. The properties of the GPIOs are controlled through registers 4Ch to ...

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WM9713L REGISTER ADDRESS 56h GPIO pins function select Table 63 Using GPIO Pins for Non-GPIO Functions w BIT LABEL DEFAULT 2 GE2 1 GPIO2 (Pin 45) Function Control 0 = Pin 45 is not controlled by GPIO logic 1 = ...

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Pre-Production POWER MANAGEMENT INTRODUCTION The WM9713L includes the standard power down control register defined by the AC’97 specification (register 26h). Additionally, it also allows more specific control over the individual blocks of the device through register Powerdown registers 3Ch and ...

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WM9713L EXTENDED POWERDOWN REGISTERS REGISTER ADDRESS 3Ch Powerdown (1) Note: When analogue inputs or outputs are disabled, they are internally connected to VREF through a large resistor (VREF=AVDD/2 except when VREF and VMID1M are both OFF). This maintains the potential ...

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Pre-Production REGISTER ADDRESS 3Eh Powerdown (2) Note: When analogue inputs or outputs are disabled, they are internally connected to VREF through a large resistor (VREF=AVDD/2 except when VREF and VMID1M are both OFF). This maintains the potential at that node ...

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WM9713L ADDITIONAL POWER MANAGEMENT Mixer output inverters: see “Mixer output Inverters” section. Inverters are disabled by default. Touchpanel Interface: see “Controlling the Touchpanel Digitiser / Power Management”. The touchpanel digitiser is OFF by default. SLEEP MODE Whenever the PR4 bit ...

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Pre-Production REGISTER MAP 00h Reset 0 SE4 SE3 02h Speaker Volume M UL ZCL 04h Headphone V olume M UL ZCL 06h OUT3/ 4 Volume M U4 ZC4 08h M ...

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... SPKRVOL Register 02h controls the output pins SPKL and SPKR. w DEFAULT DESCRIPTION 11000 Indicates a codec from Wolfson Microelectronics 0101 Indicates 18 bits resolution for ADCs and DACs 1 Indicates that the WM9713L supports bass boost 1 Indicates that the WM9713L has a headphone output ...

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Pre-Production REGISTER BIT LABEL ADDRESS 04h 15 MUL 14 ZCL 13:8 HPL VOL 7 MUR 6 ZCR 5:0 HPR VOL Register 04h controls the headphone output pins, HPL and HPR. REGISTER BIT LABEL ADDRESS 06h 15 MU4 14 ZC4 13:8 ...

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WM9713L REGISTER BIT LABEL ADDRESS 08h 15 M2H 14 M2S 12:8 MONOINVO 5:0 MONOVOL Register 08h controls the analogue output pin MONO and the analogue input pin MONOIN. REGISTER BIT LABEL ADDRESS 0Ah 15 L2H ...

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Pre-Production REGISTER BIT LABEL ADDRESS 0Ch 15 D2H 14 D2S 13 D2M 12:8 DACLVOL 4:0 DACRVOL Register 0Ch controls the audio DACs (but not AUXDAC). REGISTER BIT LABEL ADDRESS 0Eh 12:8 MICAVOL 4:0 MICBVOL Register 0Eh controls the microphone PGA ...

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WM9713L REGISTER BIT LABEL ADDRESS 12h 15 RMU 14 GRL 13:8 RECVOLL GRR 5:0 RECVOLR Register 12h controls the record volume. w DEFAULT DESCRIPTION 1 (mute) Audio ADC Input Mute Control 1 = Mute ...

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Pre-Production REGISTER BIT LABEL ADDRESS 14h 15:14 R2H 13:11 R2HVOL 10:9 R2M 8 R2MBST 6 RECBST 5:3 RECSL 2:0 RECSR Register 14h controls the.record selector and the ADC to mono mixer path. w DEFAULT DESCRIPTION 11 (mute) Record Mux to ...

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WM9713L REGISTER BIT LABEL ADDRESS 16h 15 B2H 14:12 B2HVOL 11 B2S 10:8 B2SVOL 7 B2M 6:4 B2MVOL Register 16h controls the analogue input pin PCBEEP. REGISTER BIT LABEL ADDRESS 18h 15 V2H 14:12 V2HVOL 11 V2S 10:8 V2SVOL 7 ...

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Pre-Production REGISTER BIT LABEL ADDRESS 1Ah 15 A2H 14:12 A2HVOL 11 A2S 10:8 A2SVOL 7 A2M 6:4 A2MVOL Register 1Ah controls the output signal of the auxiliary DAC. w DEFAULT DESCRIPTION 1 (mute) AUXDAC to Headphone Mixer Mute Control 1 ...

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WM9713L REGISTER BIT LABEL ADDRESS 1Ch 15:14 MONO 13:11 SPKL 10:8 SPKR 7:6 HPL 5:4 HPR 3:2 OUT3 1:0 OUT4 Register 1Ch controls the inputs to the output PGAs. w DEFAULT DESCRIPTION 00 (VMID) MONO Source Control 00 = VMID ...

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Pre-Production REGISTER BIT LABEL ADDRESS 1Eh 15:13 INV1 12:10 INV2 5 3DLC 4 3DUC 3:0 3DDEPTH Register 1Eh controls 3D stereo enhancement for the audio DACs and input muxes to the output inverters INV1 and INV2. w DEFAULT DESCRIPTION 000 ...

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WM9713L REGISTER BIT LABEL ADDRESS 20h 11:8 BASS 6 DAT 4 TC 3:0 TRBL Register 20h controls the bass and treble response of the left and right audio DAC (but not AUXDAC). w DEFAULT DESCRIPTION 0 ...

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Pre-Production REGISTER BIT LABEL ADDRESS 22h 15:14 MICCMP SEL 13:12 MPASEL 11:10 MPABST 9:8 MPBBST 7 MBOP2EN 6 MBOP1EN 5 MBVOL 4:2 MCDTHR 1:0 MCDSCTHR Register 22h controls the microphone input configuration and microphone bias and detect configuration. w DEFAULT ...

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WM9713L REGISTER BIT LABEL ADDRESS 24h 4 JIEN 3:2 DCDRVSEL 1:0 EARSPK SEL Register 24h controls the output volume mapping on headphone jack insertion. REGISTER BIT LABEL ADDRESS 26h 14 PR6 13 PR5 12 PR4 11 PR3 10 PR2 9 ...

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Pre-Production REGISTER BIT LABEL ADDRESS 28h 15:14 ID read-only 11:10 REV 9 AMAP 8 LDAC 7 SDAC 6 CDAC 3 VRM 2 SPDIF 1 DRA 0 VRA Register 28h is a read-only register that indicates to the driver which advanced ...

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WM9713L REGISTER BIT LABEL ADDRESS 2Ch all DACSR 2Eh all AUXDACSR 32h all ADCSR Note: The VRA bit in register 2Ah must be set first to obtain sample rates other than 48kHz Registers 2Ch, 2Eh 32h and control the sample ...

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Pre-Production REGISTER BIT LABEL ADDRESS 36h 15 CTRL 14:13 MODE 11:9 DIV 8 VDACOSR FSP 5:4 SEL 3:2 WL 1:0 FMT Register 36h controls the PCM codec. w DEFAULT DESCRIPTION 0 (GPIO reg) GPIO Pin Configuration Control ...

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WM9713L REGISTER BIT LABEL ADDRESS 3Ah DRS 13:12 SPSR PRE 2 COPY 1 AUDIB 0 PRO Register 3Ah Read/Write. Controls the S/PDIF output. w DEFAULT DESCRIPTION 0 S/PDIF Validity Bit 1 = ...

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Pre-Production REGISTER BIT LABEL ADDRESS 3Ch 15 PADCPD 14 VMID1M 13 TSHUT 12 VXDAC 11 AUXDAC 10 VREF 9 PLL 7 DACL 6 DACR 5 ADCL 4 ADCR 3 HPLX 2 HPRX 1 SPKX “0” corresponds to ...

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WM9713L REGISTER BIT LABEL ADDRESS 3Eh 15 MCD 14 MICBIAS 13 MONO 12 OUT4 11 OUT3 10 HPL 9 HPR 8 SPKL 7 SPKR MOIN MPA 0 MPB * “0” ...

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Pre-Production REGISTER BIT LABEL ADDRESS 40h 13 3DE 7 LB Register 40h is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the WM9713L. REGISTER BIT LABEL ADDRESS 42h 6 MONO 5 SPKL ...

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WM9713L REGISTER BIT LABEL ADDRESS 44h 14:12 S [6:4] EXT 11:8 S [3:0] EXT 7 CLKSRC 5:3 PENDIV 2 CLKBX2 1 CLKAX2 0 CLKMUX Register 44h controls clock division and muxing. w DEFAULT DESCRIPTION 000 (div 1) Hi-Fi Block Clock ...

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Pre-Production REGISTER BIT LABEL ADDRESS 15:12 N[3:0] 46h SDM 9 DIVSEL 8 DIVCTL 6:4 PGADDR 3:0 PGDATA Register 46h controls PLL clock generation. w DEFAULT DESCRIPTION 0000 (div by 1) PLL N Divide Control 0000 = Divide ...

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WM9713L REGISTER BIT LABEL ADDRESS 4Ch GCn n 4Eh GPn n 50h GSn n 52h GWn n 54h GIn n Bit definitions 15 for registers 14 4Ch to 54h ...

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Pre-Production REGISTER BIT LABEL ADDRESS 56h 8 GE8 7 GE7 6 GE6 5 GE5 4 GE4 3 GE3 2 GE2 Register 56h controls the use of GPIO pins for non-GPIO functions. REGISTER BIT LABEL ADDRESS 58h 15:8 PU 7:0 PD ...

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WM9713L REGISTER BIT LABEL ADDRESS 5Ah 15:13 COMP2DEL 8 RSTDIS 7:6 JSEL 5:4 HPMODE 3:2 DIE REV 1 WAKEEN 0 IRQ INV Register 5Ah controls several additional functions. w DEFAULT DESCRIPTION 000 (no delay) Low Battery Alarm Delay Control 000 ...

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Pre-Production REGISTER BIT LABEL ADDRESS 5Ch 15 AMUTE 14 C2REF 13:12 C2SRC 11 C1REF 10:9 C1SRC 7 AMEN 6:5 VBIAS 4 ADCO 3 HPF 1:0 ASS Register 5Ch controls several additional functions. w DEFAULT DESCRIPTION 0 DAC Automute Status (Read-Only) ...

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WM9713L REGISTER BIT LABEL ADDRESS 60h 15:12 ALCL 11:8 HLD 7:4 DCY 3:0 ATK 62h 15:14 ALCSEL 13:11 MAXGAIN 10:9 ZC TIMEOUT 7 NGAT 5 NGG 4:0 NGTH Registers 60h and 62h control the ALC and Noise Gate functions. w ...

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Pre-Production REGISTER BIT LABEL ADDRESS 64h 15 XSLE 14:12 AUXDAC SLT 11:0 AUXDAC VAL Register 64h controls the input signal of the auxiliary DAC. REGISTER BIT LABEL ADDRESS 74h 9 POLL 8 CTC 7 ADCSEL_ AUX4 6 ADCSEL_ AUX3 5 ...

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WM9713L REGISTER BIT LABEL ADDRESS 76h 9:8 CR 7:4 DEL 3 SLEN 2:0 SLT Register 76h controls the touchpanel interface measurement timing. w DEFAULT DESCRIPTION 00 (93.75Hz) Continuous Mode Conversion Rate DEL < 1111 00 = 93.75Hz 01 = 120Hz ...

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Pre-Production REGISTER BIT LABEL ADDRESS 78h 15:14 PRP 13 RPR 12 45W 11 PDEN 10 PDPOL 9 WAIT 8 PIL 7:6 MSK 5:0 RPU Register 78h controls the physical properties of the touchpanel interface. w DEFAULT DESCRIPTION 00 (disabled) Touchpanel ...

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WM9713L REGISTER BIT LABEL ADDRESS 7Ah 15 PNDN read only 14:12 ADCSRC 11:0 ADCD Registers 7Ah is a read-only register which reports the touchpanel interface status and measurement results. REGISTER BIT LABEL ADDRESS 7Ch 15:8 F7:0 read-only 7:0 S7:0 7Eh ...

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Pre-Production APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 36 Recommended External Component Diagram w WM9713L PP Rev 3.2 September 2008 123 ...

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WM9713L LINE OUTPUT The headphone outputs, HPL and HPR, can be used as stereo line outputs. The speaker outputs, SPKL and SPKR, can also be used as line outputs. Recommended external components are shown below. Figure 37 Recommended Circuit for ...

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Pre-Production DC COUPLED (CAPLESS) HEADPHONE OUTPUT In the interest of saving board space and cost, it may be desirable to eliminate the 220µF DC blocking capacitors. This can be achieved by using OUT3 as a headphone pseudo-ground, as shown below. ...

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WM9713L COMBINED HEADSET / BTL EAR SPEAKER In smartphone applications with a loudspeaker and separate ear speaker (receiver), a BTL ear speaker can be connected at the OUT3 pin, as shown below. Figure 41 Combined Headset / BTL Ear Speaker ...

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Pre-Production JACK INSERT DETECTION The circuit diagram below shows how to detect when a headphone or headset has been plugged into the headphone socket. It generates an interrupt, instructing the controller to enable HPL and HPR and disable OUT3. Figure ...

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WM9713L TYPICAL OUTPUT CONFIGURATIONS The WM9713L has three outputs capable of driving loads down to 16Ω (headphone / line drivers) – HPL, HPR and MONO - and four outputs capable of driving loads down to 8Ω (loudspeaker / line drivers) ...

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Pre-Production MONO SPEAKER Figure 46 shows a typical output configuration for mono speaker with headphones, ear speaker and hands-free operation. The table shows suggested mixer outputs to select for each output PGA for a given operating scenario. (Note the inverted ...

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WM9713L WM9713L MONO SPEAKER Figure 47 shows a typical output configuration compatible with the WM9712 for mono speaker with headphones, ear speaker and hands-free operation. The table shows suggested mixer outputs to select for each output PGA for a given ...

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Pre-Production PACKAGE DIMENSIONS FL: 48 PIN QFN PLASTIC PACKAGE EXPOSED GROUND PADDLE BOTTOM VIEW (A3) SIDE VIEW C SEATING PLANE W (A3 Exposed lead Half etch tie bar Symbols Dimensions ...

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... WM9713L IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...

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