CS4223-BS Cirrus Logic Inc, CS4223-BS Datasheet

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CS4223-BS

Manufacturer Part Number
CS4223-BS
Description
Audio CODECs 24-Bit 105dB Ster Cod w/o Vol. Con.
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4223-BS

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
CS4223-BS
Quantity:
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Part Number:
CS4223-BS
Manufacturer:
CRYSTAL
Quantity:
20 000
Part Number:
CS4223-BSZ
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Features
Cirrus Logic, Inc.
http://www.cirrus.com
105 dB Dynamic Range A/D Converters
105 dB Dynamic Range D/A Converters
110 dB DAC Signal-to-Noise Ratio (EIAJ)
Analog Volume Control (CS4224 only)
Differential Inputs / Outputs
On-chip Anti-aliasing and Output Smoothing
De-emphasis for 32, 44.1 and 48 kHz
Supports Master and Slave Modes
Single +5 V power supply
On-Chip Crystal Oscillator
3 - 5 V Digital Interface
Filters
I
24-Bit 105 dB Audio Codec with Volume Control
SDOUT
LRCK
SCLK
SDIN
RST
SCL/CCLK SDA/CDIN AD0/CS
( DIF1 )
Clock OSC
XTI XTO
( DIF0 )
Control Port
( DEM0 )
( ) = CS4223
Right
Right
DAC
DAC
ADC
ADC
Left
Left
Copyright
( DEM1 )
I C/SPI
2
Description
The CS4223/4 is a highly integrated, high performance,
24-bit, audio codec providing stereo analog-to-digital and
stereo digital-to-analog converters using delta-sigma
conversion techniques. The device operates from a sin-
gle +5 V power supply, and features low power
consumption. Selectable de-emphasis filter for 32, 44.1,
and 48 kHz sample rates is also included.
The CS4224 includes an analog volume control capable
of 113.5 dB attenuation in 0.5 dB steps. The analog vol-
ume control architecture preserves dynamic range
during attenuation. Volume control changes are imple-
mented using a “soft” ramping or zero crossing
technique.
Applications include digital effects processors, DAT, and
multitrack recorders.
ORDERING INFORMATION
(All Rights Reserved)
CS4223-KS
CS4223-BS
CS4223-DS
CS4224-KS
CDB4223/4
*
= CS4224
©
Volume
Volume
Control
Control
Cirrus Logic, Inc. 2002
V
DGND
L
*
*
MCLK
Reference
AGND
-10 to +70 °C
-40 to +85 °C
-40 to +85 °C
-10 to +70 °C
Voltage
VD
VA
AOUTL+
AOUTL-
AOUTR+
AOUTR-
AINL-
AINL+
AINR-
AINR+
CS4223
CS4224
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
Evaluation Board
DS290F1
JAN ‘03
1

Related parts for CS4223-BS

CS4223-BS Summary of contents

Page 1

... Volume control changes are imple- mented using a “soft” ramping or zero crossing technique. Applications include digital effects processors, DAT, and multitrack recorders. ORDERING INFORMATION CS4223-KS CS4223-BS CS4223-DS CS4224-KS CDB4223/4 ( DIF1 ) ( DIF0 ) ( DEM0 ) ( DEM1 ) ...

Page 2

... ANALOG CHARACTERISTICS ................................................................................................ 5 SWITCHING CHARACTERISTICS .......................................................................................... 8 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224) ..................... 9 SWITCHING CHARACTERISTICS - CONTROL PORT - I 2. TYPICAL CONNECTION DIAGRAM — CS4223 ................................................................... 11 3. TYPICAL CONNECTION DIAGRAM — CS4224 ................................................................... 12 4. REGISTER QUICK REFERENCE - CS4224 .......................................................................... 13 5. REGISTER DESCRIPTIONS - CS4224 .................................................................................. 14 5.1 ADC Control (address 01h)............................................................................................... 14 5 ...

Page 3

... Left and Right Channel Acceptance Bit (ACCR-ACCL) ................................................ 18 5.6.2 Left and Right Channel ADC Output Level (LVR and LVL) ........................................... 18 5.7 Master Clock Control (address 07h) ................................................................................. 18 5.7.1 Master Clock Control (MCK).......................................................................................... 18 6. PIN DESCRIPTIONS — CS4223 ............................................................................................ 19 7. PIN DESCRIPTIONS — CS4224 ............................................................................................ 21 8. APPLICATIONS ..................................................................................................................... 23 8.1 Overview .......................................................................................................................... 23 8 ...

Page 4

... LIST OF TABLES Table 1. Example Volume Settings ............................................................................................... 16 Table 2. Common Clock Frequencies ........................................................................................... 19 Table 3. Digital Interface Format - DIF1 and DIF0 ....................................................................... 20 Table 4. De-emphasis Control....................................................................................................... 20 Table 5. Common Clock Frequencies ........................................................................................... 21 4 CS4223 CS4224 DS290F1 ...

Page 5

... The maximum over or under voltage is limited by the input current. DS290F1 Symbol Digital VD Analog VA Digital Commercial (-KS Industrial (-BS/-DS (AGND, DGND = 0 V, all voltages with respect to 0 V.) Symbol Digital VD Analog VA (Note 1) (Note 2) (Note 2) Power Applied CS4223 CS4224 Min Nom Max Unit 4.75 5.0 5.25 V 4.75 5.0 5.25 V 2.7 5.0 5. 0 °C -40 ...

Page 6

... THD+N - -97 (1 kHz 1.9 2.0 - 100 2.3 CMRR 75 (Note (Note 4) 30 (Note 18/Fs gd_L Right t - 17/Fs gd_R ∆ 3 (Note 18/48 kHz = 375 µs. gd CS4223 CS4224 CS4223 Max Min Typ Max - - 0.0014 - - 95 105 - - 92 102 - -90 - - 2.1 1.9 2.0 2 100 - - - ...

Page 7

... Resistance 10 Capacitance - - ±0.1 - ±0.5 0 (Note 8) - 26.2 (Note 9) 70 Left t - 26/Fs gd_L Right t - 27/Fs gd_R kHz - CS4223 CS4224 CS4223 Max Min Typ Max - 97 110 - 95 105 - 92 102 - - 0.0014 -92 - - 0.1 0.5 0.65 0.35 0.5 0.65 - 110 113 ± 2.4 1 ...

Page 8

... DIGITAL CHARACTERISTICS Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage -2 Low-level Output Voltage 2 Input Leakage Current Output Leakage Current High Impedance Digital Outputs 8 Symbol Min Digital Inputs - - CS4223 CS4224 Max Unit 0 µA 10 µA DS290F1 ...

Page 9

... SCLK Period SCLK High Time SCLK Low Time SCLK rising to LRCK edge LRCK edge to SCLK rising Notes: 10. After powering up the CS4223/4, PDN should be held low for allow the power supply to settle. LRCK SCLK* SDIN SDOUT *SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1. ...

Page 10

... L Symbol f sck (Note 11) t srs (Note 12) t spi t csh t css t scl t sch t dsu (Note 13 (Note 14 (Note 14 css t scl t sch dsu t dh Figure 2. SPI Control Port Timing CS4223 CS4224 Min Max Unit - 6 MHz 41 - µs 500 - ns 1.0 - µ 100 ns - 100 all other times. ...

Page 11

... Repeated Start t high t hdst sud t sust low hdd 2 Figure Control Port Timing CS4223 CS4224 2 C MODE (CS4224) Min Max - 100 50 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 4.7 - Stop susp hdst ...

Page 12

... TYPICAL CONNECTION DIAGRAM — CS4223 Ferrite Bead +5V Supply + 1 µF 150Ω 20 2.2 nF 150Ω 19 150Ω 17 2.2 nF 150Ω Mode Selection 500 Ω Required for Master Mode only Figure 4. CS4223 Recommended Connection Diagram 12 2 Ω 0.1 µF 0.1 µ µ AINL+ ...

Page 13

... RST I2C/SPI 5 SCLK NC 4 LRCK NC 9 SDIN NC 8 SDOUT NC AGND DGND 22 7 (Also see Recommended Layout Diagram) CS4223 CS4224 0.1 µ µF Analog Filter Analog Filter External Clock Input Eliminate the crystal and capacitors when using an external clock input Audio R DSP ...

Page 14

... Control default HPDR HPDL ADMR MUTC MUTR MUTL ATT6 ATT5 ATT4 DEM1 DEM0 DSCK ACCL LVR2 LVR1 CS4223 CS4224 ADML CAL CALP CLKE SOFT Reserved RMP1 RMP0 ATT3 ATT2 ATT1 ATT0 DOF1 DOF0 DIF1 DIF0 LVR0 LVL2 LVL1 LVL0 MCK1 MCK0 ...

Page 15

... When this function is enabled, a rising edge on the reset line will initiate an offset calibration. 5.1.5 CALIBRATION STATUS (CALP) (READ ONLY) Default = Calibration done 1 - Calibration in progress DS290F1 2 C mode and write-only in SPI mode, unless otherwise noted ADMR ADML CS4223 CS4224 CAL CALP CLKE ...

Page 16

... Zero crossing is independently monitored and implemented for each channel. The ACCR and ACCL bits in the Converter Status Report register indicate when a level change has occurred for the right and left channel MUTL SOFT CS4223 CS4224 Reserved RMP1 RMP0 DS290F1 ...

Page 17

... DAC output. Binary Code 00000000 11100011 11100100 DS290F1 ATT4 ATT3 Decimal Value 0 227 228 Table 1. Example Volume Settings CS4223 CS4224 2 1 ATT2 ATT1 0 0 Volume Setting 0 dB -113.5 dB Muted 0 ATT0 0 17 ...

Page 18

... Right justified, 24-bit 11- Right justified, 20-bit Function: The required relationship between the left/right clock, serial clock and input serial data is defined by the Serial Data Input Format, and the options are detailed in Figures 8-11 DSCK DOF1 CS4223 CS4224 DOF0 DIF1 DIF0 DS290F1 ...

Page 19

... XTI = 512 Fs for Master Mode Function: The MCK bits allow for control of the Master Clock, XTI, input frequency. Note: These bits are not valid when operating in slave mode. DS290F1 LVR1 LVR0 Reserved Reserved CS4223 CS4224 LVL2 LVL2 LVL0 Reserved MCK1 MCK0 ...

Page 20

... Crystal Connections (Input/Output) - Input and output connections for the crystal used to clock the CS4223. Alternatively, a clock may be input into XTI. This is the clock source for the delta-sigma modulator and digital filters. The frequency of this clock must be either 256x, 384x, or 512x Fs in Slave Mode and 256x in Master Mode. ...

Page 21

... When high, the control port becomes operational and normal operation will occur. DS290F1 DIF0 DESCRIPTION 24-bit data 1 Left Justified 24-bit data 0 Right Justified, 24-bit Data 1 Right Justified, 20-bit Data Table 3. Digital Interface Format - DIF1 and DIF0 DEM1 De-Emphasis kHz 0 1 44.1 kHz kHz 1 1 Disabled CS4223 CS4224 FORMAT FIGURE ...

Page 22

... SDIN 9 20 SCL/CCLK 10 19 SDA/CDIN 11 18 AD0/ (kHz) XTI (MHz) 256x 32 8.1920 44.1 11.2896 48 12.2880 Table 5. Common Clock Frequencies CS4223 CS4224 NC RST AOUTL- AOUTL+ AOUTR+ AOUTR- AGND VA AINL+ AINL- I2C/SPI AINR+ AINR- NC 384x 512x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 DS290F1 ...

Page 23

... Reset (Input) - When low, the device enters a low power mode and all internal registers are reset, including the control port. When high, the control port becomes operational and normal operation will occur. DS290F1 C mode, SCL requires an external pull-up resistor according to the I CS4223 CS4224 2 C specification mode and requires specification ...

Page 24

... Fs. The de-emphasis feature is in- cluded to accommodate older audio recordings that utilize pre-emphasis as a means of noise re- duction. De-emphasis control is achieved with the DEM1/0 pins on the CS4223 or through the DEM1-0 bits in the DSP Port Mode Byte (#5) on the CS4224. 8.7 Power-up / Reset / Power Down Calibration Upon power up, the user should hold RST = 0 for approximately 10 ms ...

Page 25

... If the operation is a read, the contents of the register pointed to by the Memory Address Pointer will be output. Setting the auto in- crement bit in MAP, allows successive reads or writes of consecutive registers. Each byte is sepa- rated by an acknowledge bit. CS4223 CS4224 C Mode 25 ...

Page 26

... CHIP ADDRESS MAP 0010000 R/W MAP = Memory Address Pointer Figure 6. Control Port Timing, SPI mode ADDR R/W ACK DATA 1-8 AD0 2 Figure 7. Control Port Timing, I CS4223 CS4224 2 1 MAP2 MAP1 0 0 DATA MSB LSB byte 1 byte n ACK DATA 1-8 ACK Stop ...

Page 27

... L eft Master 24-bit data XTI=256, 384, 512 Fs (CS4223 -256 Fsonly) LRCK = kHz SCLK = eft Master Left-justified 24-bit data XTI=256, 384, 512 Fs (CS4223-256Fsonly) LRCK = kHz SCLK = 64 Fs LRCK SCLK SDATA Master Right-justified, 24-bit data XTI=256, 384, 512 Fs (CS4223-256Fsonly) LRCK = kHz SCLK = 64 Fs ...

Page 28

... clocks Master Right-justified, 20-bit data XTI=256, 384, 512Fs (CS4223-256Fsonly) LRCK = kHz SCLK = 64 Fs Input Right-justified, 20-bit data XTI = 256, 384, 512 Fs LRCK = kHz SCLK = 64 Fs Figure 11. Serial Audio Format 3 Figure 12. Optional Input Buffer 150 Ω + AINR+ 2 µF CS4223/4 AINR- 4.7 µF + 0.1 µ ...

Page 29

... Gain µ - Figure 15. De-emphasis Curve DS290F1 Figure 14. 2- and 3-Pole Butterworth Filters µs F2 Frequency Figure 16. Hybrid Analog/Digital Attenuation CS4223 CS4224 Analog Digital 0 Signal Noise 0 -113.5 Attenuation (dB) 29 ...

Page 30

... ADC/DAC FILTER RESPONSE Figure 17. ADC Filter Response Figure 19. ADC Transition Band Figure 21. DAC Passband Ripple 30 CS4223 CS4224 Figure 18. ADC Passband Ripple Figure 20. DAC Filter Response Figure 22. DAC Transition Band DS290F1 ...

Page 31

... The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSB's of the output from mid-scale with the selected inputs tied to a com- mon potential. For the DAC's, the differential output voltage with mid-scale input code. Units are in volts. DS290F1 CS4223 CS4224 31 ...

Page 32

... JEDEC #: MO-150 Controlling Dimension is Millimeters CS4223 CS4224 ∝ END VIEW L MILLIMETERS NOM MAX -- -- 2.13 0.15 0.25 1.75 1.88 -- 0.38 10.20 10.50 7.80 8 ...

Page 33

Notes • ...

Page 34

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