CS4205-KQ Cirrus Logic Inc, CS4205-KQ Datasheet
CS4205-KQ
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CS4205-KQ Summary of contents
Page 1
... Coupling the CS4205 with a PCI audio accelerator or core logic supporting the AC ’97 interface implements a cost effective, superior quality audio solution. The CS4205 surpasses PC 99, PC 2001, and AC ’97 2.1 au- dio quality standards. ORDERING INFO CS4205-KQZ, Lead Free 48-pin TQFP 9x9x1.4 mm AC-LINK AND AC '97 REGISTERS PWR PCM_DATA TEST ...
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... DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. 2 CS4205 DS489PP4 ...
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... Vendor ID2 Register (Index 7Eh) ................................................................................... 53 6. SERIAL DATA PORTS ........................................................................................................... 54 6.1 Overview .......................................................................................................................... 54 6.2 Multi-Channel Expansion ................................................................................................. 54 6.3 Digital Docking ................................................................................................................. 55 6.4 Serial Data Formats ......................................................................................................... PORT ................................................................................................................................. 57 8. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 58 9. EXCLUSIVE FUNCTIONS ...................................................................................................... 58 10. POWER MANAGEMENT ..................................................................................................... 59 10.1 AC ’97 Reset Modes ...................................................................................................... 59 10.1.1 Cold Reset ........................................................................................................ 59 10.1.2 Warm Reset ...................................................................................................... 59 DS489PP4 .................................................................................................... 24 CS4205 3 ...
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... Figure 3. Clocks ............................................................................................................................ 10 Figure 4. Data Setup and Hold...................................................................................................... 11 Figure 5. PR4 Powerdown and Warm Reset ................................................................................ 11 Figure 6. Test Mode ...................................................................................................................... 11 Figure 7. AC-link Connections....................................................................................................... 12 Figure 8. CS4205 Mixer Diagram.................................................................................................. 14 Figure 9. Digital Signal Path Overview.......................................................................................... 15 Figure 10. Analog Centric Mode.................................................................................................... 17 Figure 11. Digital Centric Mode..................................................................................................... 17 Figure 12. Host Processing Mode ................................................................................................. 17 Figure 13. Multi-Channel Mode ..................................................................................................... 17 Figure 14 ...
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... Figure 27. Differential 1 VRMS CD Input ...................................................................................... 64 Figure 28. Microphone Input ......................................................................................................... 65 Figure 29. PC_BEEP Input ........................................................................................................... 65 Figure 30. Modem Connection...................................................................................................... 65 Figure 31. Stereo Output............................................................................................................... 66 Figure 32. +5V Analog Voltage Regulator .................................................................................... 66 Figure 33. Conceptual Layout for the CS4205 when in XTAL or OSC Clocking Modes............... 69 Figure 34. Pin Locations for the CS4205 ...................................................................................... 70 Figure 35. CS4205 Reference Design .......................................................................................... 79 DS489PP4 CS4205 5 ...
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... Table 20. Internal Error Sources and Correction Methods ...............................................50 Table 21. ZV Port Control/Status Register Index..............................................................51 Table 22. Device ID with Corresponding Part Number .....................................................53 Table 23. Serial Data Formats and Compatible DACs/ADC’s for the CS4205 ................56 Table 24. Powerdown PR Bit Functions ...........................................................................60 Table 25. Powerdown PR Function Matrix for the CS4205 ..............................................61 Table 26 ...
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... A-A D-A A-D SNR D-A THD+N A-A D-A (all inputs) A-D (Note 4) (Note 4) (Note 4) refers to the digital output pin loading. DL CS4205 = 25° C, ambient =100 kΩ/ AL CS4205-KQZ Min Typ Max 0.91 1.00 - 0.91 1.00 - 0.283 0.315 - 0.091 0.10 - 0.0283 0.0315 - 0.91 1.0 1 ...
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... V Digital +5 V Digital Analog (Supplies, Inputs, Outputs) (Except Supply Pins) (Except Supply Pins) (Power Applied) (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) Symbol +3.3 V Digital DVdd1, DVdd2 +5 V Digital DVdd1, DVdd2 Analog AVdd1, AVdd2 CS4205 CS4205-KQZ Min Typ Max 730 - - 5 - 2.3 2.4 2.5 ...
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... Output Leakage Current (Tri-stated AC-link outputs) Output buffer drive current BIT_CLK, SPDO/SDO2 SDATA_IN, EAPD/SCLK, GPIO0/LRCLK, GPIO1/SDOUT, GPIO2/SDI1, GPIO3/SDI2, GPIO4/SDI3 DS489PP4 (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) Symbol Min 2. 3. -10 -10 - (Note 3. 4. -10 -10 - (Note 4) - CS4205 Typ Max Unit - 0. 3. 0.03 0. µ µ 0. 4. 0.03 0. µ µ ...
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... T clk_low F sync T sync_period T sync_high T sync_low isetup T ihold T irise T ifall (Note 4) T orise (Note 4) T ofall T s2_pdown T 1.0 sync_pr4 T 162.8 sync2clk setup2rst (Note 4) T off CS4205 = 25° C, ambient Typ Max Unit µ µs - 4.0 - µ µs - 62.5 - µ 12.288 - MHz - 81 750 ...
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... BIT_CLK RESET# Vdd BIT_CLK SYNC CODEC_READY Figure 2. Codec Ready from Start-up or Fault Condition BIT_CLK T orise SYNC T irise DS489PP4 T rst_low T vdd2rst# Figure 1. Power Up Timing T sync2crd clk_high clk_low clk_period T ifall T T sync_high sync_low T sync_period Figure 3. Clocks CS4205 T rst2clk T ifall 11 ...
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... Slot 1 SDATA_OUT Write to 0x20 SDATA_IN SYNC RESET# SDATA_OUT, SYNC SDATA_IN, BIT_CLK isetup Figure 4. Data Setup and Hold Slot 2 Data PR4 Don't Care T s2_pdown Figure 5. PR4 Powerdown and Warm Reset T setup2rst T off Figure 6. Test Mode T ihold T T sync_pr4 sync2clk Hi-Z CS4205 DS489PP4 ...
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... During each au- dio frame, data is passed bi-directionally between the CS4205 and the controller. The input frame is driven from the CS4205 on the SDATA_IN line. The output frame is driven from the controller on the SDATA_OUT line ...
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... Sample Rate Converters The sample rate converters (SRC) provide high ac- curacy digital filters supporting sample frequencies other than 48 kHz to be captured from the CS4205 or played from the controller. AC ’97 requires sup- port for two audio rates (44.1 and 48 kHz) and four modem rates (8, 9.6, 13.714, and 16 kHz). In addi- ® ...
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... INPUT MIXER Σ Σ ANALOG STEREO OUTPUT MIXER MONO MIX STEREO TO SELECT MONO MIXER Σ 1/2 Σ STEREO TO MONO MIXER 1/2 Figure 8. CS4205 Mixer Diagram CS4205 DAC DIRECT MASTER MODE VOLUME OUTPUT MUTE BUFFER MONO OUT MONO SELECT VOLUME OUTPUT MUTE ...
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... DIGITAL SIGNAL PATHS The CS4205 includes a number of internal digital signal path options. Figure 9 shows the principal signal flow options through one channel of the de- vice. Four commonly used signal flow modes are detailed in the following sections. The signal flow modes are controlled through the bits in the AC Mode Control Register (Index 5Eh) ...
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... The processed signal is sent to the DACs, bypassing the analog mixer using DAC direct mode. In host processing mode, the playback and capture paths are completely separate inside the CS4205. 3.4 Multi-channel mode is detailed in Figure 13. This mode is an extension of any of the other three ...
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... MICS VOL VOL I²S VOL IN1 Σ I²S DIG VOL IN2 EFX I²S VOL IN3 ZV ASRC VOL Signal Processing Engine Figure 13. Multi-Channel Mode CS4205 LINE_OUT Σ MONO_OUT S/PDIF OUT SPDS LINE_OUT DDM Σ MONO_OUT I²S VOL OUT1 I²S VOL OUT2 DS489PP4 ...
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... The first bit position in a new se- rial data frame is F0 and the last bit position in the serial data frame is F255. When SYNC goes active (high) and is sampled active by the CS4205 (on the falling edge of BIT_CLK), both devices are syn- chronized to a new serial data frame. The data on the SDATA_OUT pin at this clock edge is the final bit of the previous frame’ ...
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... AC-Link Serial Data Output Frame In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4205 from the AC ’97 controller. Figure 14 illustrates the serial port timing. The PCM playback data being passed to the CS4205 is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC ’ ...
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... Not Implemented GPIO[4:0] GPIO Pin Control. The GPIO[4:0] bits control the CS4205 GPIO pins configured as outputs. Write accesses using GPIO pin control bits configured as outputs will be reflected on the GPIO pin output on the next AC-link frame. Write accesses using GPIO pin control bits con- figured as inputs will have no effect and are ignored. If the GPOC bit in the Misc. Crystal Con- trol Register (Index 60h) is ‘ ...
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... AC-Link Serial Data Input Frame In the serial data input frame, data is passed on the SDATA_IN pin from the CS4205 to the AC ’97 con- troller. The data format for the input frame is very similar to the output frame. Figure 14 on page 19 illus- trates the serial port timing. ...
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... GPIO[4:0] GPIO Pin Status. The GPIO[4:0] bits reflect the status of the CS4205 GPIO pins configured as inputs. The pin status of GPIO pins configured as outputs will be reflected back on the GPIO[4:0] bits of input Slot 12 in the next frame. The output GPIO pins are controlled by the GPIO[4:0] pin control bits in output Slot 12 ...
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... BIT_CLK clock period after the previous SYNC assertion. Upon loss of synchronization with the controller, the CS4205 will ‘clear’ the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the CS4205 will ignore all register reads and writes and will discontinue the transmission of PCM capture data ...
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... D13 D12 D11 D10 E13 E12 E11 E10 Table 2. Register Overview for the CS4205 CS4205 ID5 0 ID3 ID2 0 0 MR5 MR4 MR3 MR2 MR1 0 MM5 MM4 MM3 MM2 MM1 TR3 TR2 TR1 0 0 PV3 PV2 PV1 PV0 0 0 GN4 GN3 GN2 ...
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... Ph24 Ph23 Ph22 Ph21 Ph20 Ph11 Ph10 Ph9 Ph8 Table 3. Indirectly Addressed Register Overview CS4205 Default 0 0 GR5 GR4 GR3 GR2 GR1 GR0 0 0 GR5 GR4 GR3 GR2 GR1 GR0 0 0 GR5 GR4 GR3 GR2 GR1 GR0 0 0 GR5 GR4 GR3 GR2 GR1 GR0 ...
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... The data in this register is read-only data. Any write to this register causes a Register Reset of the audio control (Index 00h - 3Ah) and Cirrus Logic defined (Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4205. 5.2 Master Volume Register (Index 02h) ...
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... BA0 0 0 TR3..TR0 Gain BA3..BA0 Level 0000 +10.5 dB 0001 +9 dB … ... 0110 +1.5 dB 0111 0 dB 1000 -1.5 dB ... ... 1101 -9 dB 1110 -10.5 dB 1111 bypass Table 5. Tone Control Values CS4205 MM5 MM4 MM3 MM2 MM1 TR3 TR2 TR1 DS489PP4 D0 MM0 D0 TR0 ...
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... Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is + -34.5 dB attenuation. See Table 7 on page 31 for further attenuation levels. Default 8008h. This value corresponds attenuation and Mute ‘set’. DS489PP4 D10 D10 CS4205 PV3 PV2 PV1 PV0 GN4 GN3 GN2 GN1 GN0 29 ...
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... Table 6. Microphone Input Gain Values CS4205 GN4 GN3 GN2 GN1 10dB = 1, 20dB = 1 +42.0 dB +40.5 dB ... +31.5 dB +30.0 dB +28.5 dB ... -4.5 dB DS489PP4 D0 GN0 ...
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... Table 7. Analog Mixer Input Gain Values Register Index Function 10h Line In Volume 12h CD Volume 14h Video Volume 16h Aux Volume 18h PCM Out Volume Table 8. Analog Mixer Input Gain Register Index GR4 GR3 GR2 CS4205 D1 D0 GR1 GR0 31 ...
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... This value selects the Mic input for both channels. 32 D10 SL2 SL1 SL0 0 0 Sx2 - Sx0 Record Source 000 Mic 001 CD Input 010 Video Input 011 Aux Input 100 Line Input 101 Stereo Mix 110 Mono Mix 111 Phone Input Table 9. Input Mux Selection CS4205 SR2 SR1 DS489PP4 D0 SR0 ...
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... This value corresponds gain and Mute ‘set’. DS489PP4 D10 GL2 GL1 GL0 0 0 Gx3 - Gx0 Gain Level 1111 +22.5 dB … … 0001 +1.5 dB 0000 0 dB Table 10. Record Gain Values D10 CS4205 GR3 GR2 GR1 GM3 GM2 GM1 D0 GR0 D0 GM0 33 ...
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... Each step corresponds to 1.5 dB gain adjustment, with a total available range from -22.5 dB attenuation. The recommended starting point for listening is -12 dB center attenuation and -4.5 dB depth attenuation, a register value of 070Ch. 34 D10 MIX MS LPBK 0 D10 CR2 CR1 CR0 0 0 CS4205 DP3 DP2 DP1 DS489PP4 D0 0 ...
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... The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular sec- tion of the CS4205 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must be checked before writing to any mixer registers. See Section 10, Power Management, for more information on the powerdown functions ...
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... ID[1:0] Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the CS4205 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4205 is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins and the current clocking scheme, see Table 27 on page 63. ...
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... Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default values. The SRC data path is flushed and the Slot Request bits for the currently active DAC slots will be fixed at ‘0’. Default 4000h DS489PP4 D10 MADC CS4205 VRM VRA 37 ...
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... Index Table 11. Audio Sample Rate Control Register Index Sample Rate (Hz) 8,000 9,600 11,025 13,714 16,000 22,050 24,000 32,000 44,100 48,000 Table 12. Directly Supported SRC Sample Rates for the CS4205 38 D10 SR9 SR8 SR7 SR6 SRC 2Ch PCM Front DAC Rate 32h ...
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... ID[1:0] Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the CS4205 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4205 is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins and the current clocking scheme, see Table 27 on page 63. ...
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... The upper 11 bits of this register always return ‘0’. 40 D10 GCx GPx Function Configuration 0 0 Output CMOS Drive 0 1 Output Open Drain 1 0 Input Active Low 1 1 Input Active High (default) Table 13. GPIO Input/Output Configurations D10 CS4205 GP4 GP3 GP2 GP1 GS4 GS3 GS2 GS1 DS489PP4 D0 GP0 D0 GS0 ...
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... AC-link wakeup if and only if the AC-link was powered down. Once the controller has re-established communication with the CS4205 following a Warm Reset, it will continue to signal the wakeup event through the GPIO_INT bit of input Slot 12 until the AC ’97 controller clears the inter- rupt-causing bit in the GPIO Pin Status Register (Index 54h) ...
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... Extended Audio ID Register (Index 28h). Refer to Table 14 for the slot mapping configura- tions. SM[1:0] Slot Map. The SM[1:0] bits define the Slot Mapping for the CS4205 when the AMAP bit is ‘cleared’. Refer to Table 14 for the slot mapping configurations. SDOS[1:0] Serial Data Output Source Select. The SDOS[1:0] bits control the source of data routed to the CS4205 first serial data output port. Table 15 on page 43 lists the available source options reserved source is selected, the serial output data will be fixed to ‘ ...
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... Table 14. Slot Mapping for the CS4205 Serial Data L/R Capture Output Source Source (CAPS[1:0]) (SDOS[1:0]) L/R ADCs SDOUT slots reserved reserved Digital Mixer Digital Mixer Digital Effects Digital Effects Table 15. Digital Signal Source Selects CS4205 Slot Assignments SDO2 SDOUT ADC SPDIF for ...
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... Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit is ‘set’, the CS4205 will mute all analog outputs for the duration of loss of SYNC. If this bit is ‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4205 ex- pects to sample SYNC ‘ ...
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... When ‘set’, the sampling frequency is 44.1 kHz. The actual rate at which S/PDIF data are being transmitted solely depends on the master clock frequency of the CS4205. The Fs bit is merely an indicator to the S/PDIF receiver. L Generation Status. The L bit is mapped to bit 15 of the channel status block. For category codes 001xxxx, 0111xxx and 100xxxx, a value of ‘ ...
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... All ports will use the same format. See Table 16 for available formats. Default 0000h 46 D10 SDI3 SDF1 SDF0 Serial Data Format Left Justified 1 0 Right Justified, 20-bit data 1 1 Right Justified, 16-bit data Table 16. Serial Data Format Selection CS4205 SDI2 SDI1 SDO2 SDSC SDF1 SDF0 DS489PP4 D0 ...
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... D[15:0] Special Feature Data. This register is an indexed data port for the special feature registers (In- dex 6E, Address 00h - 0Fh) which control advanced subsystems of the CS4205, such as digital mixer settings, effects engine parameters, ZV Port control, and internal error condition signaling. Before using any of these functions, the correct index value must be written to the Special Fea- ture Address Register (Index 6Ch) ...
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... This value corresponds gain and Mute ‘set’. The Serial Data Port Volume Control Registers are listed in Table 18. 48 D10 GL2 GL1 GL0 0 Register Address Function 06h SDOUT Volume 07h SDO2 Volume Table 18. Serial Port Volume Control Register Index GR5 GR4 GR3 GR2 CS4205 D1 D0 GR1 GR0 DS489PP4 ...
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... Table 19. Volume Change Modes and EQ Filter Selects DS489PP4 D10 GL2 Volume Change Mode immediately on zero crossings soft ramp (1/8 dB step per frame) 1/8 dB step per zero crossing GL1 GL0 GR3 GR2 GR1 Low Pass High Pass Filter Filter kHz kHz 100 Hz 20 kHz reserved reserved CS4205 D0 GR0 49 ...
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... Table 20. Internal Error Sources and Correction Methods 50 D10 AMOR AROR ALOR 0 0 Correction Method GL[3:0] bits in reg 1Ch GR[3:0] bits in reg 1Ch GM[3:0] bits in reg 1Eh GL[5:0] bits in reg 6Eh, addr 00h-05h GR[5:0] bits in reg 6Eh, addr 00h-05h GL[3:0] bits in reg 6Eh, addr 08h CS4205 DS489PP4 D0 0 ...
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... Ph10 Ph9 Ph8 Ph7 Ph6 in Register Address Function 0Eh ZV Port Control/Stat 1 0Fh ZV Port Control/Stat 2 Table 21. ZV Port Control/Status Register Index D10 E10 Ph17 Ph16 Ph15 Ph14 Ph13 Ph5 Ph4 Ph3 Ph2 Ph1 = Fs *Ph/16,777,216, where Fs out CS4205 Ph12 Ph0 is 48 kHz. out ...
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... The BDI bit in input slot logic OR of all bits in this register ANDed with their cor- responding bit in the BDI Config Register (Index 6Eh, Address 0Ch). After handling an event, the driver should clear it by writing a ‘0’ to the corresponding bit of this register. 52 CS4205 DS489PP4 ...
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... Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII ‘Y’ char- acter. DID[2:0] Device ID. With a value of DID[2:0] = 101, these bits specify the audio codec is a CS4205. REV[2:0] Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is ‘A’. ...
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... DACs in a system have the same phase response, maintaining the accuracy of spatial cues. In the CS4205, the volume of the serial port data is controlled with the Serial Data Port Volume Con- trol Registers (Index 6Eh, Address 06h - 07h). However, there is no SRC available on this data the responsibility of the controller or host soft- ware to provide this functionality if desired ...
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... In all cases, LRCLK will be synchronous with Fs, and SCLK will (BIT_CLK/4). Se- rial data is transitioned by the CS4205 on the falling edge of SCLK and latched by the DACs on the next rising edge. Serial data is shifted out MSB first in all supported formats, but LRCLK polarity as well as data justification, alignment, and resolution vary ...
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... Justification 0 0 negative left justified 0 1 positive left justified 1 0 positive right justified 1 1 positive right justified Table 23. Serial Data Formats and Compatible DACs/ADC’s for the CS4205 Left Channel LRCK SCLK SDATA Left Channel LRCK SCLK SDATA LRCK ...
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... ZSCLK, ZLR- CLK, and ZSDATA. Although the ZV Port speci- fication calls for SCLK running at 32 Fs, the CS4205 supports any SCLK from 128 Fs. In all cases, only the first 16 bits of each channel will be recovered from the incoming serial data stream ...
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... For further information on S/PDIF recommended transformers see application note AN134: AES and S/PDIF Recommended Transformers [4]. 9. EXCLUSIVE FUNCTIONS Some of the digital pins on the CS4205 have mul- tiplexed functionality. These functions are mutual- ly exclusive and cannot be requested at the same time. The following pairs of functions are mutually exclusive: • ...
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... This is done in accordance with the minimum timing specifications in the AC ’97 Seri- al Port Timing section on page 10. Once de-assert- ed, all of the CS4205 registers will be reset to their default power-on states and the BIT_CLK and SDATA_IN signals will be reactivated. 10.1.2 Warm Reset A Warm Reset allows the AC-link to be reactivated without losing information in the CS4205 registers ...
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... The PR[5:0] bits in this register control the internal powerdown states of the CS4205. Power- down control is available for individual subsections of the CS4205 by asserting any PRx bit or any com- bination of PRx bits. All powerdown states except PR4 and PR5 can be resumed by clearing the cor- responding PRx bit ...
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... AC-Link off (PR4) Internal Clocks off (PR5) Digital off (PR4+PR5) All off (PR3+PR4+PR5) RESET Table 26. Power Consumption by Powerdown Mode for the CS4205 1 Assuming standard resistive load for transformer coupled coaxial S/PDIF output (Rload = 292 Ohm, DVdd = 3.3 V) (Rload = 415 Ohm, DVdd = 5 V). General ...
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... MHz BIT_CLK output; see Table 27 on page 63 for additional de- tails. In PLL mode, the CS4205 is configured as a primary codec independent of the state of the ID[1:0]# pins. If 24.576 MHz is chosen as the ex- ternal clock input (ID[1:0]# inputs both pulled high or left floating), the PLL is disabled and the clock is used directly ...
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... External 48.000 0 XTAL 24.576 1 BIT_CLK 12.288 2 BIT_CLK 12.288 3 BIT_CLK 12.288 Table 27. Clocking Configurations for the CS4205 CS4205 PLL Application Notes Active No clock generator driving XTL_IN Yes external clock source driving XTL_IN Yes loop filter connected to XTL_OUT Yes No crystal connected to XTL_IN, XTL_OUT ...
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... Replicate this circuit for the Video and Aux in- puts. This design attenuates the input by 6 dB, bringing the signal from the PC 99 specified the CS4205 maximum allowed 1 V RMS 12.1.2 CD Input The CD line-level input has an extra pin, CD_GND, providing a pseudo-differential input for both CD_L and CD_R ...
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... PC Beep Input The PC_BEEP input is useful for mixing the output of the “beeper” (timer chip), provided in most PCs, with the other audio signals. When the CS4205 is held in reset, PC_BEEP is passed directly to the line output. This allows the system sounds or “beeps” available before the AC ’97 interface has been activated ...
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... CS4205 supplies power to all the analog circuitry and should be con- nected to +5 VA/AGND. The AVdd2 and AVss2 pins are not used on the CS4205 and may be left floating or tied to +5 VA/AGND for backwards compatibility. The DVdd2/DVss2 digital power/ground pin pair on the CS4205 should be connected to the same digital supply as the controller’ ...
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... Reference Design See Section 16 for a CS4205 reference design. DS489PP4 CS4205 67 ...
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... GROUNDING AND LAYOUT Figure 33 on page 69 shows the conceptual layout for the CS4205 in XTAL or OSC clocking modes. The decoupling capacitors should be located phys- ically as close to the pins as possible. Also, note the connection of the REFFLT decoupling capacitors to the ground return trace connected directly to the ground return pin, AVss1 ...
Page 69
... Via to +5VA 0.1 µF Y5V AVss2 DVdd1 Via to +5VD or +3.3VD Figure 33. Conceptual Layout for the CS4205 when in XTAL or OSC Clocking Modes DS489PP4 Vrefout to via 1000 pF NPO AFLT3 AFLT1 AFLT2 REFFLT AVdd2 Via to Analog Ground Digital Ground Via to Digital Ground Pin 1 0.1 µF ...
Page 70
... PIN DESCRIPTIONS 48 DVdd1 1 XTL_IN 2 XTL_OUT 3 DVss1 4 SDATA_OUT 5 6 BIT_CLK DVss2 7 SDATA_IN 8 DVdd2 9 SYNC 10 RESET# 11 PC_BEEP CS4205 Figure 34. Pin Locations for the CS4205 LINE_OUT_R 35 LINE_OUT_L 34 ZSCLK 33 ZSDATA 32 ZLRCLK 31 AFLT3 30 AFLT2 29 AFLT1 28 Vrefout 27 REFFLT 26 AVss1 25 AVdd1 CS4205 DS489PP4 ...
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... AC-coupled to analog ground. CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20 These inputs form a stereo input pair to the CS4205 intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. ...
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... VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17 These inputs form a stereo input pair to the CS4205 intended to be used for the audio signal output of a video device. The maximum allowable input internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or AC-coupled to analog ground ...
Page 73
... SDATA_IN - AC-Link Serial Data Output Stream from AC ’97, Output, Pin 8 This output signal transmits the status information and digital audio input streams from the ADCs. The data is clocked out of the CS4205 on the rising edge of BIT_CLK. A series terminating resistor of 47 Ω should be connected on this signal close to the CS4205. ...
Page 74
... Section 11, Clocking, for additional details. ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46 These pins select the Codec ID for the CS4205, as well as determine the rate of the incoming clock in PLL mode. They are only sampled after the rising edge of RESET#. These pins are internally pulled up to the digital supply voltage and should be left floating for logic ‘ ...
Page 75
... ZSDATA - ZV Port Serial Data, Input, Pin 33 This pin receives two’s complement MSB-first serial audio data for the Zoomed Video Port. The data is clocked into the CS4205 by the ZSCLK, and the channel is determined by ZLRCLK. The signal must conform to the ZV Port Specification. ...
Page 76
... AVss2 should be isolated from digital ground currents AVdd2, AVss2 - Analog Supply Voltage 2 / Analog Ground 2, Pins 38 and 42 The AVdd2 and AVss2 pins are not used on the CS4205 and may be left floating or tied and AGND for backwards compatibility 76 ...
Page 77
... Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is the CS4205. DAC Refers to a single Digital-to-Analog converter in the CS4205. “DACs” refers to the stereo pair of Digital-to-Analog converters. The CS4205 DACs have 20-bit resolution defined as dB relative to full-scale. The “A” indicates an A weighting filter was used. ...
Page 78
... SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS4205 operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 kHz. Total Harmonic Distortion plus Noise (THD+N) THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level ...
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... REFERENCE DESIGN 2 GND DS489PP4 + + 38 AVdd2 25 AVdd1 42 AVss2 26 AVss1 1 DVdd1 9 DVdd2 + + + + + CS4205 3 XTL_OUT 2 XTL_IN + + 79 ...
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... PC 2001 System Design Guide, Version 1.0, November 2000 http://www.pcdesguide.org/pc2001/default.htm ® 9) Intel 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub, June 1999 http://developer.intel.com/design/chipsets/datashts/290655.htm ® 10) Intel 82801BA (ICH2) I/O Controller Hub, October 2000 http://developer.intel.com/design/chipsets/datashts/290687.htm ® 11) Intel 82801CAM (ICH3-M) I/O Controller Hub, July 2001 http://developer.intel.com/design/chipsets/datashts/290716.htm 80 CS4205 DS489PP4 ...
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... CS4205 A A1 MILLIMETERS MIN NOM MAX --- 1.40 0.05 0.10 0.17 0.22 8.70 9.0 BSC 6.90 7.0 BSC 8.70 9.0 BSC 6.90 7 ...