DS26502LN

Manufacturer Part NumberDS26502LN
DescriptionTimers & Support Products E1-T1-J1-64KCC BITS Element 64kHz - G.70
ManufacturerMaxim Integrated Products
TypeClock Recovery
DS26502LN datasheet
 

Specifications of DS26502LN

Supply Voltage (max)3.46 VSupply Voltage (min)3.13 V
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Current85 mA
Package / CaseLQFP-64  
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GENERAL DESCRIPTION
The DS26502 is a building-integrated timing-
supply (BITS) clock-recovery element. It also
functions as a basic T1/E1 transceiver. The
receiver portion can recover a clock from T1,
E1, 64kHz composite clock (64KCC), and
6312kHz synchronization timing interfaces. In
T1 and E1 modes, the Synchronization Status
Message (SSM) can also be recovered. The
transmit portion can directly interface to T1, E1,
or 64KCC synchronization interfaces as well as
source the SSM in T1 and E1 modes. The
DS26502 can translate between any of the
supported inbound synchronization clock rates to
any supported outbound rate. A separate output
is provided to source a 6312kHz clock. The
device is controlled through a parallel, serial, or
hardware controller port.
APPLICATIONS
BITS Timing
Rate Conversion
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS26502L
0°C to +70°C
DS26502LN
-40°C to +85°C
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
T1/E1/J1/64KCC BITS Element
FEATURES
G.703 2048kHz Synchronization Interface
Compliant
G.703 64kHz Centralized (Option A) and
Codirectional Timing Interface Compliant
G.703 Appendix II 64kHz and 6312kHz
Japanese Synchronization Interface
Compliant
Interfaces to Standard T1/J1 (1.544MHz) and
E1 (2.048MHz)
Interface to CMI-Coded T1/J1 and E1
Short- and Long-Haul Line Interface
Transmit and Receive T1 and E1 SSM
Messages with Message Validation
T1/E1 Jitter Attenuator with Bypass Mode
Fully Independent Transmit and Receive
Functionality
Internal Software-Selectable Receive- and
Transmit-Side Termination for
75Ω/100Ω/110Ω/120Ω T1, E1, and
Composite Clock Interfaces
Monitor Mode for Bridging Applications
Accepts 16.384MHz, 12.8MHz, 8.192MHz,
4.096MHz, 2.048MHz, or 1.544MHz Master
Clock
64kHz, 8kHz, and 400Hz Outputs in
Composite Clock Mode
8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
64 LQFP
Serial (SPI) Control Port
64 LQFP
Hardware Contr-ol Mode
Provides LOS, AIS, and LOF Indications
Through Hardware Output Pins
Fast Transmitter-Output Disable Through
Device Pin for Protection Switching
IEEE 1149.1 JTAG Boundary Scan
3.3V Supply with 5V Tolerant Inputs and
Outputs
1 of 125
DESIGN KIT AVAILABLE
DS26502
REV: 042208

DS26502LN Summary of contents

  • Page 1

    ... TEMP RANGE PIN-PACKAGE DS26502L 0°C to +70°C DS26502LN -40°C to +85°C Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. ...

  • Page 2

    FEATURES .......................................................................................................................7 1.1 G .....................................................................................................................................7 ENERAL 1 ...........................................................................................................................7 INE NTERFACE 1 ITTER TTENUATOR 1 RAMER ORMATTER 1 EST AND IAGNOSTICS 1 ............................................................................................................................8 ONTROL ORT 2. SPECIFICATIONS COMPLIANCE ...................................................................................9 3. ...

  • Page 3

    NFORMATION EGISTERS 10. I/O PIN CONFIGURATION OPTIONS ............................................................................52 11. T1 SYNCHRONIZATION STATUS MESSAGE ..............................................................55 11 RIENTED 11.2 T BOC .........................................................................................................................55 RANSMIT 11.3 R BOC ...........................................................................................................................56 ECEIVE 12. E1 SYNCHRONIZATION STATUS MESSAGE ...

  • Page 4

    ECEIVE IDE 20 RANSMIT IDE 21. REVISION HISTORY ....................................................................................................124 22. PACKAGE INFORMATION ..........................................................................................125 22.1 64-P LQFP (56-G4019-001).................................................................................................125 IN .......................................................................................120 HARACTERISTICS .....................................................................................122 HARACTERISTICS 4 of 125 ...

  • Page 5

    Figure 3-1. Block Diagram ........................................................................................................................11 Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ........................................................................12 Figure 3-3. Transmit PLL Clock Mux Diagram..........................................................................................12 Figure 3-4. Master Clock PLL Diagram ....................................................................................................13 Figure 13-1. Basic Network Connection ...................................................................................................77 Figure 13-2. Typical Monitor Application ..................................................................................................79 ...

  • Page 6

    Table 2-1. T1-Related Telecommunications Specifications........................................................................9 Table 2-2. E1-Related Telecommunications Specifications .....................................................................10 Table 5-1. LQFP Pinout ............................................................................................................................23 Table 6-1. Transmit Clock Source ............................................................................................................26 Table 6-2. Internal Termination ................................................................................................................26 Table 6-3. E1 Line Build-Out ....................................................................................................................27 Table 6-4. T1 Line Build-Out ....................................................................................................................27 Table ...

  • Page 7

    FEATURES 1.1 General 64-pin, 10mm x 10mm LQFP package 3.3V supply with 5V-tolerant inputs and outputs Evaluation kits IEEE 1149.1 JTAG Boundary Scan Driver source code available from the factory 1.2 Line Interface Requires a single master clock (MCLK) ...

  • Page 8

    Framer/Formatter Full receive and transmit path transparency T1 framing formats include D4 and ESF E1 framing formats include FAS and CRC4 Detailed alarm and status reporting with optional interrupt support RLOF, RLOS, and RAIS alarms interrupt on change of ...

  • Page 9

    SPECIFICATIONS COMPLIANCE The DS26502 meets all applicable sections of the latest telecommunications specifications including those listed in the following tables. Table 2-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface ANSI T1.231: Digital Hierarchy–Layer 1 in Service Performance ...

  • Page 10

    Table 2-2. E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048kbps ITUT G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps ITUT G.772 ITUT G.775 ITUT G.823 ...

  • Page 11

    BLOCK DIAGRAMS Figure 3-1. Block Diagram MCLK MASTER CLOCK CLOCK RTIP DATA LIU LIU RRING - DATA RLOS RAIS TNEGO TPOSO TTIP TX LIU TRING THZE TCLKO JTAG PORT JTAG PORT JTAG PORT JTAG PORT JTMS ...

  • Page 12

    Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) CLOCK FROM RX + DATA LIU - DATA CLOCK DATA LIU - DATA Figure 3-3. Transmit PLL Clock Mux Diagram RECOVERED CLOCK TCLK PIN JA CLOCK JITTER ATTENUATOR ENABLED ...

  • Page 13

    Figure 3-4. Master Clock PLL Diagram 13 of 125 ...

  • Page 14

    PIN FUNCTION DESCRIPTION 4.1 Transmit PLL NAME TYPE Transmit PLL Output. This pin can be selected to output the 1544kHz, PLL_OUT O 2048kHz, 64kHz, or 6312kHz output from the internal TX PLL or the internal signal, TX CLOCK. See ...

  • Page 15

    Receive Side NAME TYPE Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), 6312 kHz RCLK O (G.703 Synchronization Interface kHz (Composite Clock) clock. Receive Sync/8kHz Clock T1/E1 Mode: An extracted pulse, one RCLK wide, is output at this ...

  • Page 16

    Controller Interface NAME TYPE Active-Low Interrupt/Jitter Attenuator Clock Select 0 INT INT/ I/O the status registers. Active-low open-drain output. JACKS0 JACKS0: Hardware Mode: Jitter Attenuator Clock Select 0. Set this pin high for T1 mode operation when either a ...

  • Page 17

    NAME TYPE Data Bus D[5] or Address/Data Bus AD[5]/Receive Framing Mode Select Bit 1 A[5]: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as the data bus D[5]. AD[5]/ I/O RMODE1 AD[5]: In multiplexed bus operation (BIS[1:0] = ...

  • Page 18

    NAME TYPE Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select 3/Master Out-Slave In A[1]: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as the data bus D[1]. AD[1]/ AD[1]: In multiplexed bus operation (BIS[1:0] = 00), this ...

  • Page 19

    NAME TYPE Address Bus Bit A[4]/Serial Port Clock Phase Select/Line Build-Out Select 2 A4: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[4]. In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and should ...

  • Page 20

    NAME TYPE Read Input-Data Strobe/Receive Mode Select Bit RD(DS)/ = 01. See the bus timing diagrams. I RMODE2 RMODE2: In Hardware Mode (BIS[1:0] = 11), this pin selects the receive side operating mode. Chip Select/Remote Loopback Enable ...

  • Page 21

    JTAG NAME TYPE JTAG Clock. This clock input is typically a low frequency (less than 10MHz) JTCLK I 50% duty cycle clock signal. JTAG Mode Select (with Pullup). This input signal is used to control the JTMS I JTAG ...

  • Page 22

    Power NAME TYPE Digital Positive Supply. 3.3V ±5%. Should be tied to the RVDD and TVDD DVDD — pins. Receive Analog Positive Supply. 3.3V ±5%. Should be tied to the DVDD and RVDD — TVDD pins. Transmit Analog Positive ...

  • Page 23

    PINOUT Table 5-1. LQFP Pinout PIN TYPE PARALLEL PORT 1 I/O AD2 2 I/O AD3 3 I/O AD4 4 I/O AD5 5 I/O AD6 6 I/O AD7 7, 24, I DVDD 58 8, 22, I DVSS ...

  • Page 24

    PIN TYPE PARALLEL PORT 18 O TCLKO 19 O TNEGO 20 O TPOSO 21 I TSER 23 I/O TS_8K_4 25 O RCLK 26 O RS_8K 27 O 400HZ 28 O RSER 29 O RAIS 30 O RLOF_CCE 31 I — ...

  • Page 25

    PIN TYPE PARALLEL PORT 59 I BIS1 (DS (R/ I/O AD0 64 I/O AD1 MODE SERIAL HARDWARE PORT BIS1 BIS1 Bus Interface Select Mode 1 Parallel Port Mode: Active-Low Chip ...

  • Page 26

    HARDWARE CONTROLLER INTERFACE In Hardware Controller mode, the parallel and serial port pins are reconfigured to provide direct access to certain functions in the port. Only a subset of the device’s functionality is available in hardware mode. Each register ...

  • Page 27

    Line Build-Out Table 6-3. E1 Line Build-Out PIN 13 PIN 12 PIN 75Ω with high return loss (Note 120Ω with high return ...

  • Page 28

    Transmitter Operating Modes Table 6-6.Transmit Path Operating Mode TMODE3 TMODE2 TMODE1 PIN 62 PIN 48 PIN ...

  • Page 29

    Table 6-8. MCLK Pre-Scaler for E1 Mode MPS1 MPS0 PIN 16 PIN 6.7 Other Hardware Controller Mode Features Table 6-9. Other Operational Modes ...

  • Page 30

    PROCESSOR INTERFACE The DS26502 is controlled via a nonmultiplexed (BIS[1: multiplexed (BIS[1:0] = 00) parallel bus. There is also a serial bus mode option, as well as a hardware mode of operation. The bus interface ...

  • Page 31

    CS is removed removed before all 8 bits of the data are read, the remaining data will be lost removed before all 8 bits of data are written to the part, ...

  • Page 32

    Register Map Table 7-2. Register Map Sorted By Address ADDRESS TYPE 00 R/W Test Reset Register 01 R/W I/O Configuration Register 1 02 R/W I/O Configuration Register 2 03 R/W T1 Receive Control Register 1 04 R/W T1 Receive ...

  • Page 33

    ADDRESS TYPE 44 R/W Transmit Remote Alarm Bits 45 R/W Transmit Sa4 Bits 46 R/W Transmit Sa5 Bits 47 R/W Transmit Sa6 Bits 48 R/W Transmit Sa7 Bits 49 R/W Transmit Sa8 Bits 4A R/W Transmit Sa Bit Control Register ...

  • Page 34

    Power-Up Sequence The DS26502 contains an on-chip power-up reset function, which automatically clears the writeable register space immediately after power is supplied to the device. The user can issue a chip reset at any time. Issuing a reset will ...

  • Page 35

    Mode Configuration Register Register Name: MCREG Register Description: Mode Configuration Register Register Address: 08h Bit # 7 6 Name TMODE3 TMODE2 Default TMODE3 TMODE2 Mode PIN 62 PIN 48 Bit Receive Mode Configuration ...

  • Page 36

    Bits Transmit Mode Configuration (TMODE[3:0]). Used to select the operating mode of the transmit path for the DS26502. TMODE3 TMODE2 TMODE1 ...

  • Page 37

    Register Name: TPCR Register Description: Transmit PLL Control Register Register Address: 09h Bit # 7 6 Name TPLLOFS1 TPLLOFS0 Default Mode For more information on all the bits in the Transmit PLL control register, refer ...

  • Page 38

    Interrupt Handling Various alarms, conditions, and events in the DS26502 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All STATUS registers can be programmed to produce interrupts. Each status register has an ...

  • Page 39

    Information Registers Information registers operate the same as status registers except they cannot cause interrupts. INFO3 register is a read-only register and it reports the status of the E1 synchronizer in real time. INFO3 information bits are not latched, ...

  • Page 40

    T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS26502 is configured via a set of five control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26502 has been ...

  • Page 41

    Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 Name — — Default Mode Bit 0: Receive Side D4 Yellow Alarm Select (RD4YM zeros in ...

  • Page 42

    Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 Name TJC TFPT Default RMODEx 0 Mode PINS Bit 0:Transmit Yellow Alarm (TYEL not transmit yellow alarm ...

  • Page 43

    Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 Name TB8ZS TFSE Default HBE 1 Mode PIN 55 Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS ...

  • Page 44

    Register Name: T1CCR Register Description: T1 Common Control Register Register Address: 07h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 for proper ...

  • Page 45

    Table 8-1. T1 Alarm Criteria ALARM Blue Alarm (AIS) (Note 1) Yellow Alarm (RAI) D4 Bit-2 Mode (T1RCR2 12th F-bit Mode (T1RCR2 this mode is also referred to as the “Japanese Yellow Alarm”) ESF Mode ...

  • Page 46

    E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS26502 is configured via a set of two control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26502 has been ...

  • Page 47

    Table 9-1. E1 Sync/Resync Criteria FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS FAS present in frame N and and FAS not present in frame CRC4 Two valid MF alignment words found within 8ms CAS ...

  • Page 48

    E1 Information Registers Register Name: INFO2 Register Description: Information Register 2 Register Address: 12h Bit # 7 6 Name — — Default Mode Bit 0: CAS Resync Criteria Met Event (CASRC). Set when two ...

  • Page 49

    Table 9-2. E1 Alarm Criteria ALARM SET CRITERIA RLOF An RLOF condition exists on power-up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated via E1RCR.0 RLOS 255 or 2048 ...

  • Page 50

    Register Name: SR2 Register Description: Status Register 2 Register Address: 16h Bit # 7 6 Name RYELC RAISC Default Mode Bit 0: Receive Loss of Frame Condition (RLOF). Set when the DS26502 is not synchronized ...

  • Page 51

    Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 17h Bit # 7 6 Name RYELC RAISC Default Mode Bit 0: Receive Loss of Frame Condition (RLOF interrupt masked 1 = ...

  • Page 52

    I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 Name — RSMS2 Default Mode Bit 0: Output Data Format (ODF bipolar ...

  • Page 53

    Table 10-1. TS_8K_4 Pin Functions TRANSMIT IOCR1.3 IOCR1.2 MODE T1/E1 0 T1/E1 0 T1/E1 0 T1/E1 0 64KCC 0 64KCC 0 64KCC 1 64KCC 1 Table 10-2. RLOF_CCE Pin Functions RECEIVE IOCR1.4 RLOF_CCE PIN FUNCTION MODE T1/E1 0 T1/E1 1 ...

  • Page 54

    Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 Name RCLKINV TCLKINV Default Mode Bits Unused, must be set = 0 for proper operation. Bit ...

  • Page 55

    T1 SYNCHRONIZATION STATUS MESSAGE The DS26502 has a BOC controller to handle SSM services in T1 mode. Table 11-1. T1 SSM Messages QUALITY LEVEL 1 Stratum 1 Traceable 2 Synchronized Traceablity Unknown 3 Stratum 2 Traceable 4 Stratum 3 ...

  • Page 56

    Receive BOC The receive BOC function is enabled by setting BOCC The RFDL register will now operate as the receive BOC message and information register. The lower six bits of the RFDL register (BOC message bits) are ...

  • Page 57

    Register Name: BOCC Register Description: BOC Control Register Register Address: 1Fh Bit # 7 6 Name — — Default Mode Bit 0: Send BOC (SBOC). Set = 1 to transmit the BOC code placed in ...

  • Page 58

    Register Name: RFDL (RFDL register bit usage when BOCC Register Description: Receive FDL Register Register Address: 50h Bit # 7 6 Name — — Default Mode Bit 0: BOC Bit 0 (RBOC0) Bit ...

  • Page 59

    Register Name: SR3 Register Description: Status Register 3 Register Address: 18h Bit # 7 6 Name RAIS-CI LOTC Default Mode Bit 0: Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a ...

  • Page 60

    Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 19h Bit # 7 6 Name RAIS-CI LOTC Default Mode Bit 0: Receive BOC Detector Change-of-State Event (RBOC interrupt masked 1 = ...

  • Page 61

    Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ah Bit # 7 6 Name — RSA1 Default Mode Bit 0: Receive Align Frame Event (RAF). (E1 only) Set every 250µs at the beginning ...

  • Page 62

    Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Bh Bit # 7 6 Name — RSA1 Default Mode Bit 0: Receive Align Frame Event (RAF interrupt masked 1 = interrupt ...

  • Page 63

    Register Name: TFDL Register Description: Transmit FDL Register Register Address: 51h Bit # 7 6 Name TFDL7 TFDL6 Default Mode Note: Also used to insert Fs framing pattern in D4 framing mode. The transmit FDL ...

  • Page 64

    E1 SYNCHRONIZATION STATUS MESSAGE The DS26502 provides access to both the transmit and receive Sa/Si bits. In E1, the Sa bits are used to transmit and receive the SSM. The primary method to access the Sa (and Si) bits ...

  • Page 65

    Register Name: RSiAF Register Description: Receive Si Bits of the Align Frame Register Address: 58h Bit # 7 6 Name SiF0 SiF2 Default Mode Bit 0: Si Bit of Frame 14(SiF14) Bit 1: Si Bit ...

  • Page 66

    Register Name: RRA Register Description: Receive Remote Alarm Register Address: 5Ah Bit # 7 6 Name RRAF1 RRAF3 Default Mode Bit 0: Remote Alarm Bit of Frame 15(RRAF15) Bit 1: Remote Alarm Bit of Frame ...

  • Page 67

    Register Name: RSa5 Register Description: Receive Sa5 Bits Register Address: 5Ch Bit # 7 6 Name RSa5F1 RSa5F3 Default Mode Bit 0: Sa5 Bit of Frame 15(RSa5F15) Bit 1: Sa5 Bit of Frame 13(RSa5F13) Bit ...

  • Page 68

    Register Name: RSa7 Register Description: Receive Sa7 Bits Register Address: 5Eh Bit # 7 6 Name RSa7F1 RSa7F3 Default Mode Bit 0: Sa7 Bit of Frame 15(RSa7F15) Bit 1: Sa7 Bit of Frame 13(RSa7F13) Bit ...

  • Page 69

    Register Name: TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: 42h Bit # 7 6 Name TsiF0 TsiF2 Default Mode Bit 0: Si Bit of Frame 14(TsiF14) Bit 1: Si Bit ...

  • Page 70

    Register Name: TRA Register Description: Transmit Remote Alarm Register Address: 44h Bit # 7 6 Name TRAF1 TRAF3 Default Mode Bit 0: Remote Alarm Bit of Frame 15(TRAF15) Bit 1: Remote Alarm Bit of Frame ...

  • Page 71

    Register Name: TSa5 Register Description: Transmit Sa5 Bits Register Address: 46h Bit # 7 6 Name TSa5F1 TSa5F3 Default Mode Bit 0: Sa5 Bit of Frame 15(TSa5F15) Bit 1: Sa5 Bit of Frame 13(TSa5F13) Bit ...

  • Page 72

    Register Name: TSa7 Register Description: Transmit Sa7 Bits Register Address: 48h Bit # 7 6 Name TSa7F1 TSa7F3 Default Mode Bit 0: Sa7 Bit of Frame 15(TSa7F15) Bit 1: Sa7 Bit of Frame 13(TSa7F13) Bit ...

  • Page 73

    Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: 4Ah Bit # 7 6 Name SiAF SiNAF Default Mode Bit 0: Additional Bit 8 Insertion Control Bit (Sa8 not ...

  • Page 74

    Alternate Sa/Si Bit Access Based on Double-Frame On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and Si bit locations. The RAF and RNAF registers are updated on ...

  • Page 75

    Register Name: RNAF Register Description: Receive Non-Align Frame Register Register Address: 57h Bit # 7 6 Name Si 1 Default Mode Bit 0: Additional Bit 8 (Sa8) Bit 1: Additional Bit 7 (Sa7) Bit 2: ...

  • Page 76

    Register Name: TNAF Register Description: Transmit Non-Align Frame Register Register Address: 41h Bit # 7 6 Name Si 1 Default 0 1 Bit 0: Additional Bit 8 (Sa8) Bit 1: Additional Bit 7 (Sa7) Bit 2: Additional Bit 6 (Sa6) ...

  • Page 77

    LINE INTERFACE UNIT (LIU) The LIU in the DS26502 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which generates waveshapes and drives the network line; and the jitter attenuator. These three sections are controlled ...

  • Page 78

    LIU Operation The LIU interfaces the T1, E1, 64KCC, and 6312kHz signals to the various types of network media through coupling transformers. The LIU transmit and receive functions are independent. For example, the receiver can mode ...

  • Page 79

    Receive G.703 Section 13 Synchronization Signal The DS26502 can receive a 2.048MHz square-wave synchronization clock as specified in Section 13 of ITU G.703. To use the DS26502 in this mode, set the mode configuration bits in the Mode Configuration ...

  • Page 80

    The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode, the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the automatic gain mode, ...

  • Page 81

    The jitter attenuator can also be disabled (in effect, removed) by setting the DJA bit (LIC1.1). Either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin ...

  • Page 82

    LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Address: 30h Bit # 7 6 Name L2 L1 Default Mode PIN 13 PIN 12 Bit 0: Transmit Power-Down (TPD) 0 ...

  • Page 83

    T1 Mode DSX 133 feet)/0dB CSU DSX-1 (133 to 266 feet DSX-1 (266 to 399 feet DSX-1 (399 to 533 feet ...

  • Page 84

    Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 31h Bit # 7 6 Name JACKS1 LIRST Default Mode Bit 0: Custom Line Driver Select (CLDS). Setting this bit to a one will ...

  • Page 85

    Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 32h Bit # 7 6 Name CMIE CMII Default Mode Bit 0: Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern at TTIP ...

  • Page 86

    Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 33h Bit # 7 6 Name MPS1 MPS0 Default MPS1 MPS0 Mode PIN 16 PIN 15 Bits Receive Termination Select (RT0 to RT2) ...

  • Page 87

    Register Name: INFO1 Register Description: Information Register 1 Register Address: 11h Bit # 7 6 Name — — Default Mode Bits Receive Level Bits (RL0 to RL3). Real-time bits. RL3 RL2 RL1 ...

  • Page 88

    Register Name: SR1 Register Description: Status Register 1 Register Address: 14h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 for proper operation. ...

  • Page 89

    Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 15h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 for proper ...

  • Page 90

    Recommended Circuits Figure 13-4. Software-Selected Termination, Metallic Protection F1 TX TIP S3 TX RING F2 RX TIP S4 RX RING Table 13-1. Component List (Software-Selected Termination, Metallic Protection) NAME F1 and F2 1.25A slow blow fuse S1 and S2 ...

  • Page 91

    Figure 13-5. Software-Selected Termination, Longitudinal Protection F1 TX TIP RING TIP RING F4 Table 13-2. Component List (Software-Selected Termination, Longitudinal Protection) NAME 1.25A slow blow fuse ...

  • Page 92

    Figure 13-6. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 Figure 13-7. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ...

  • Page 93

    Figure 13-8. Jitter Tolerance (T1 Mode) 1K 100 10 1 0.1 1 Figure 13-9. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DS26502 Tolerance TR 62411 (Dec. 90) ITU-T G.823 10 100 1K FREQUENCY (Hz) DS26502 Tolerance ...

  • Page 94

    Figure 13-10. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 Figure 13-11. Jitter Attenuation (E1 Mode) 0dB -20dB -40dB -60dB 1 DS26502 T1 MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area Prohibited Area DS26502 E1 MODE 10 100 ...

  • Page 95

    LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Control Register Register Address: 20h Bit # 7 6 Name — — Default Mode Bits Unused, must be set = 0 ...

  • Page 96

    SYNCHRONIZATION INTERFACE The 64kHz synchronization interface conforms to G.703 requirements for Centralized Timing (option A), Contradirectional Timing, and 64kHz Appendix II. It consists of a composite clock, where a 64kHz clock signal is generated or decoded, along with ...

  • Page 97

    Transmit 64kHz Synchronization Interface Operation In the transmit path, the framer will generate the appropriate AMI waveform with the correct bipolar violations as described by G.703 8kHz signal is present on the TS_8K_4 pin, the bipolar violations ...

  • Page 98

    SYNCHRONIZATION INTERFACE The DS26502 has a 6312kHz Synchronization Interface mode of operation that conforms with Appendix II.2 of G.703, with the exception that the DS26502 transmits a square wave as opposed to the sine wave that is defined ...

  • Page 99

    JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26502 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26502 contains the following as required by IEEE ...

  • Page 100

    TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 17-2. Test-Logic-Reset Upon power-up, the TAP controller will be in the test-logic-reset ...

  • Page 101

    Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and will initiate a scan sequence for the ...

  • Page 102

    Figure 17-2. TAP Controller State Diagram Test Logic 1 Reset 0 Run Test/ 0 Idle 1 1 Select DR-Scan Capture DR 0 Shift Exit DR 0 Pause Exit2 ...

  • Page 103

    Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the shift-IR state, the instruction shift register will be connected between JTDI ...

  • Page 104

    IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the capture-DR ...

  • Page 105

    Table 17-4. Boundary Scan Control Bits CELL # NAME 0 AD1 1 AD1_7_CTRL 2 AD0 3 AD0_CTRL 4 WR_RW 5 RD_DS BIS1 8 BIS0 9 BTS 10 THZE 11 TMODE1 12 TMODE2 13 PLL_CLK 14 INT 15 ...

  • Page 106

    CELL # NAME 29 TNEGO observe_only 30 TCLKO observe_only 31 TCLK observe_only 32 ALE_A7 observe_only 33 A6 observe_only 34 A5 observe_only 35 A4 observe_only 36 A3 observe_only 37 A2 observe_only 38 A1 observe_only 39 A0 observe_only 40 AD7 41 AD6 ...

  • Page 107

    FUNCTIONAL TIMING DIAGRAMS 18.1 Processor Interface 18.1.1 Parallel Port Mode See the AC Timing section. 18.1.2 SPI Serial Port Mode Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 SCK CS MOSI 1 0 ...

  • Page 108

    Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 SCK CS MOSI MSB MISO Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 SCK CS ...

  • Page 109

    Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 SCK CS MOSI MSB MISO Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 SCK CS ...

  • Page 110

    ... Operating Temperature Range for DS26502L…………………………………………………………0°C to +70°C Operating Temperature Range for DS26502LN……………………………………………-40°C to +85°C (Note 1) Storage Temperature Range… ...

  • Page 111

    ... Table 19-5. DC Characteristics = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) PARAMETER SYMBOL Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) Note 6: 0.0V < V < Applied to INT when three-stated. Note 7: = 3.3V ±5 MIN TYP -1 -1 +4.0 OL 111 of 125 = -40° ...

  • Page 112

    ... Capacitive test loads are 40pF for bus signals and 20pF for all others. 20.1 Multiplexed Bus Table 20-1. AC Characteristics, Multiplexed Parallel Port = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) (Note 1, Figure PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Times R/W Hold Time ...

  • Page 113

    Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) ALE t ASD AD0-AD7 Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00) ALE t ASD RD t ASD WR ...

  • Page 114

    Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1: ASD AD0-AD7 (read) CS AD0-AD7 (write) A8 & ASH t ASED t RWS t t DDR ASL t AHL ...

  • Page 115

    ... Nonmultiplexed Bus Table 20-2. AC Characteristics, Non-Mux Parallel Port = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) (Note 1, Figure PARAMETER Setup Time for A0 to A7, Valid to CS Active Setup Time for CS Active to Either RD, WR Active Delay Time from Either Active to Data Valid ...

  • Page 116

    Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1: 0ns min RD Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1: ...

  • Page 117

    Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1: 0ns min. DS Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1: ...

  • Page 118

    ... Serial Bus Table 20-3. AC Characteristics, Serial Bus = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) (Note 1, Figure 20-8 DIAGRAM CHARACTERISTIC (NOTE 3) NUMBER Operating Frequency (NOTE 2) Slave 1 Cycle Time: Slave 2 Enable Lead Time 3 Enable Lag Time Clock (CLK) High Time 4 Slave ...

  • Page 119

    Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1: INPUT CLK INPUT CPOL = 0 2 CLK INPUT CPOL = 1 8 MISO INPUT 6 MOSI OUTPUT NOTE: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST ...

  • Page 120

    ... Receive Side AC Characteristics Table 20-4. Receive Side AC Characteristics = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) (Note 1 and Figure PARAMETER RCLK Period RCLK Pulse Width RCLK Pulse Width RCLK to RSER Delay RCLK to RS_8K, 400Hz Delay The timing parameters in this table are guaranteed by design (GBD). ...

  • Page 121

    Figure 20-10. Receive Timing, T1, E1, 64KCC Mode RCLK t D1 RSER RS_8K 1 RS_8K 2 400HZ 3 NOTES: 1) RS_8K OUTPUT MODE. 2) RS_8K OUTPUT IN 64KCC MODE. 3) 400Hz OUTPUT ACTIVE ONLY IN 64KCC ...

  • Page 122

    Transmit Side AC Characteristics Table 20-5. Transmit Side AC Characteristics = 3.3V ±5 -40°C to +85°C.) (Note 1 and DD A PARAMETER TCLK Period TCLK Pulse Width TCLK Rise and Fall Times TX CLOCK Setup ...

  • Page 123

    Figure 20-11. Transmit Timing, T1, E1, 64KCC Mode t R TCLK RCLK, JA CLOCK 4 PLL_OUT TX CLOCK 3 TSER TS_8K_4 1 TS_8K_4 2 (REFER TO THE TRANSMIT PLL BLOCK DIAGRAM, NOTE 1: TS_8K_4 IN OUTPUT MODE. NOTE 2: TS_8K_4 ...

  • Page 124

    ... Replaced Figure 13-4 and Figure 13-5 to show 10μF cap on TTIP. In the Absolute Maximum Ratings (Section 19), added Note 1: Specifications at -40 100507 production tested. to Operating Temp Range for DS26502LN. Renumbered notes for Table 19-1 to Table 19-5. Clarified RITD and TITD descriptions. For E1TS description, changed 0 = 120Ω and 1 = 75Ω 75Ω and 121707 1 = 120Ω ...

  • Page 125

    ... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. 125 of 125 © 2008 Maxim Integrated Products ...