SPL505YC264BT Silicon Laboratories Inc, SPL505YC264BT Datasheet - Page 16

• Manufacturer Part Number: SPL505YC264BT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC264BT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used to synchro-
nously stop and start the PCI outputs while the rest of the clock
generator continues to function. The set-up time for capturing
PCI_STP# going LOW is 10 ns (t
clocks will not be affected by this pin if their corresponding
control bit in the SMBus register is set to allow them to be free
running.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level.
CPUC(Free Running)
CPUT(Free Running)
CPUC(Stoppable)
CPUT(Stoppable)
CPU_STOP#
DOT96T
DOT96C
SRC 100MHz
S R C 100M H z
PCI_STP#
P C I_S T P #
PD#
PCI_F
P C I_F
CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
P C I
PCI
SU
). (See Figure 5.) The PCIF
Tsu
T su
Figure 6. PCI_STP# Deassertion Waveform
Figure 5. PCI_STP# Assertion Waveform
Tdrive_SRC
SPL505YC256BT/
SPL505YC256BS
Page 16 of 27
1.8mS