SPL505YC264BT Silicon Laboratories Inc, SPL505YC264BT Datasheet - Page 6

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SPL505YC264BT

Manufacturer Part Number
SPL505YC264BT
Description
Clock Generators & Support Products CK505 v0.85
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SPL505YC264BT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Rev 1.4 March 21, 2007
Byte 0: Control Register 0
Byte 1: Control Register 1
Byte 2: Control Register 2
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
@Pup
@Pup
HW
HW
HW
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
SRC_MAIN_SEL
PLL1_SS_DC
PLL3_SS_DC
RESERVED
PD_Restore
PLL3_CFB3
PLL3_CFB2
PLL3_CFB1
PLL3_CFB0
SRC0_SEL
SATA_SEL
PCIF0_OE
iAMT_EN
PCI_SEL
PCI4_OE
PCI3_OE
REF_OE
USB_OE
Name
Name
FS_C
FS_B
FS_A
CPU Frequency Select Bit, set by HW
CPU Frequency Select Bit, set by HW
CPU Frequency Select Bit, set by HW
Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled, Sticky 1
RESERVED
Select source for SRC clock,
0 = SRC_MAIN = PLL1, PLL3_CFB Table applies
1 = SRC_MAIN = PLL3, PLL3_CFB Table does not apply
Select source of SATA clock
Save Config. In powerdown
Select for SRC0 or DOT96, 0 = SRC0, 1 = DOT96
Select for down or center SS,
0 = Down spread, 1 = Center spread
Select for down or center SS,
0 = Down spread, 1 = Center spread
Bit 4:1 only apply when SRC_SEL=0
0000 = PLL3 Disable Default
0001 = 100 MHz 0.5% SSC Stby
0010 = 100 MHz 0.5% SSC
0011 = 100 MHz 1.0% SSC
0100 = 100 MHz 1.5% SSC
0101 = 100 MHz 2.0% SSC
0110 = RESERVED
0111 = RESERVED
1000 = RESERVED
1001 = RESERVED
1010 = RESERVED
1011 = 27MHz_NSS on SE1 and SE2
1100 = 25MHz on SE1 and SE2
1101 = 25MHz on SE1 and SE2 Disabled
config to HW mode 3)
1110 = RESERVED
1111 = RESERVED
Select PCI Clock source from PLL1 or SRC_MAIN
0 = PLL1, 1 = SRC_MAIN
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
Output enable for USB
0 = Output Disabled, 1 = Output Enabled
Output enable for PCIF0
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI4, 0 = Output Disabled, 1 = Output Enabled
Output enable for PCI3, 0 = Output Disabled, 1 = Output Enabled
0 = SATA SRC_MAIN, 1= SATA PLL2
0 = Config. Cleared, 1 = Config. Saved
Description
Description
PLL3 OFF, SRC1 = SRC_MAIN
PLL3 ON, SRC1 = SRC_MAIN
Only SRC1 sourced from PLL3
Only SRC1 sourced from PLL3
Only SRC1 sourced from PLL3
Only SRC1 sourced from PLL3
SPL505YC256BT/
SPL505YC256BS
(set whenPCI3/CFB0 is set high to
Note: SE clocks required to be
enabled through Byte 8 Bit1:0
Page 6 of 27

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