SPL505YC264BT Silicon Laboratories Inc, SPL505YC264BT Datasheet - Page 9

• Manufacturer Part Number: SPL505YC264BT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC264BT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
Byte 9 Control Register 9
Byte 10 Control Register 10
Byte 11 Control Register 11
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
HW_Pin
@Pup
@Pup
HW
HW
HW
0
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
TEST_MODE_ENTRY
PCIF0_STP_CTRL
TEST_MODE_SEL
SRC5_EN_STRAP
CPU1_STP_CRTL
CPU0_STP_CRTL
25MHz_EN_SE1
SRC_DIV_EN
CPU_DIV_EN
TME_STRAP
PCI_DIV_EN
RESERVED
PCI3_CFG1
PCI3_CFG0
REF_DSC1
IO_VOUT2
IO_VOUT1
IO_VOUT0
PLL3_EN
PLL2_EN
Name
Name
Allows control of PCIF0 with assertion of PCI_STOP#
0 = Free running PCIF, 1 = Stopped with PCI_STOP#
Trusted mode enable strap status, 0 = normal, 1 = no overclocking
REF drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
Allow entry into test mode
0=Normal operation, 1=Enter test mode
IO_VOUT[2,1,0]
000 = 0.3V
001 = 0.4V
010 = 0.5V
011 = 0.6V
100 = 0.7V
101 = 0.8V, Default
110 = 0.9V
111 = 1.0V
Read only bit for SRC5_EN_STRAP
0 = CPU/PCI_STOP enabled, 1 = SRC5 pair enabled
PLL3 Enabled
0 = PLL3 disabled, 1 = PLL3 enabled
PLL2 Enabled
0 = PLL2 disabled, 1 = PLL2 enabled
SRC Divider Enabled
0 = SRC Divider disabled, 1 = SRC Divider enabled
PCI Divider Enabled
0 = PCI Divider disabled, 1 = PCI Divider enabled
CPU Divider Enabled
0 = CPU Divider disabled, 1 = CPU Divider enabled
Allow control of CPU1 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
Allow control of CPU0 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
25MHz Output Enabled applies to Powerdown / M1
(Only applies when PCI3/CGFG0 strap is set high to enter HW mode 3)
0 = 25MHz disabled in Powerdown / M1
1 = 25MHz enabled in Powerdown / M1; Sticky 1
RESERVED
CGF1
PCI3/
0
0
1
1
CGF0
PCI3/
0
1
0
1
0 -Def
Mode
1
2
3
CPU / SRC / PCI33
Output
CPU
CPU
CPU
PLL1
Description
Description
Center
Center USB/25M
Down
Down
SSC
SPL505YC256BT/
SPL505YC256BS
Output
USB
USB
USB
Page 9 of 27
PLL2
SSC
NA
NA
NA
NA
SRC/PCI33
SRC/PCI33
SRC/PCI33
Output
--
PLL3
Down
Down
Down
SSC
--