SPL505YC256BT Silicon Laboratories Inc, SPL505YC256BT Datasheet

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SPL505YC256BT

Manufacturer Part Number
SPL505YC256BT
Description
Clock Generators & Support Products CK505 v0.85
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SPL505YC256BT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SPL505YC256BT
Quantity:
20
Part Number:
SPL505YC256BTT
Manufacturer:
SPECTRALI
Quantity:
18 150
Rev 1.4 March 21, 2007
2200 Laurelwood Road, Santa Clara, CA 95054
Features
Block Diagram
• Compliant to Intel
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz Differential SRC clocks
• 100 MHz Differential LCD clock
• 96 MHz Differential Dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• 25 MHz WOL or PATA clock
• 27 MHz non-spread Video Clock
®
CK505
Clock Generator for Intel
Tel:(408) 855-0555
Table 1. Output Configuration Table
Pin Configuration
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select input
• I
• Triangular Spread Spectrum profile for maximum
• 3.3V Power supply/0.7V for Diff IOs
• 56-pin TSSOP and SSOP package
x2/x3
CPU
SRC1# / LCD_100#/SE2
electromagnetic interference (EMI) reduction
SRC1 / LCD_100/SE1
2
SRC3# / OE#_1/4_B
C support with readback capabilities
PCI_0 / OE#_0/2_A
PCI_1 / OE#_1/4_A
SRC3/OE#_0/2_B
PCI_4 / SRC5_EN
SRC0# / DOT96#
PCIF_0 / ITP_EN
Fax:(408) 855-0550
SRC2# / SATA#
SRC0 / DOT96
VDD_PLL3_IO
PCI_3 / CFG0*
USB_48 / FSA
VDD_SRC_IO
SRC2 / SATA
PCI_2 / TME
VDD_PLL3
VSS_PLL3
VSS_SRC
x8/12
VDD_PCI
VSS_PCI
SRC
VDD_48
VSS_48
VDD_IO
VSS_IO
SRC4#
SRC4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SPL505YC256BT/
PCI REF DOT96 USB_48M
x6
SPL505YC256BS
* Internal Pull-Down
®
x 1
Bearlake Chipset
www.SpectraLinear.com
x 1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SCLK
SDATA
REF0 / FSC / TEST_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FSB / TEST_MODE
CK_PW RGD / PW RDW N#
VDD_CPU
CPU0
CPU0#
VSS_CPU
CPU1
CPU1#
VDD_CPU_IO
IO_VOUT
SRC8 / CPU2_ITPT
SRC8# / CPU2_ITPC
VDD_SRC_IO
SRC7 / OE#_8
SRC7# / OE#_6
VSS_SRC
SRC6
SRC6#
VDD_SRC
SRC5 / PCI_STOP#
SRC5# / CPU_STOP#
Page 1 of 27
x 1
LCD
x1

Related parts for SPL505YC256BT

SPL505YC256BT Summary of contents

Page 1

... SRC0 / DOT96 SRC0# / DOT96# VSS_IO VDD_PLL3 SRC1 / LCD_100/SE1 SRC1# / LCD_100#/SE2 VSS_PLL3 VDD_PLL3_IO SRC2 / SATA SRC2# / SATA# VSS_SRC SRC3/OE#_0/2_B SRC3# / OE#_1/4_B VDD_SRC_IO SRC4# Tel:(408) 855-0555 Fax:(408) 855-0550 SPL505YC256BT/ SPL505YC256BS ® Bearlake Chipset PCI REF DOT96 USB_48M SCLK 2 55 SDATA 3 54 ...

Page 2

... PWR 0.7V power supply for SRC outputs. O, DIF 100 MHz Differential serial reference clocks. O, DIF 100 MHz Differential serial reference clocks. I/O, 3.3V tolerant input for stopping PCI and SRC outputs /100 MHz Differential Dif serial reference clocks. SPL505YC256BT/ SPL505YC256BS Description Page ...

Page 3

... Selects test mode if pulled to V Refer to DC Electrical Specifications table for V fications. I/O SMBus compatible SDATA. I SMBus compatible SCLOCK. SPL505YC256BT/ SPL505YC256BS Description Note: CPU1 is an iAMT clock in iAMT mode Note: CPU1 is an iAMT clock in iAMT mode when CK_PWRGD is asserted HIGH. IHFS_C ...

Page 4

... Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h) . Description SPL505YC256BT/ SPL505YC256BS USB PCI REF (MHz) (MHz) ...

Page 5

... Acknowledge from slave 27:20 Data byte–8 bits 28 Acknowledge from slave 29 Stop Control Registers Byte 0: Control Register 0 Bit @Pup Name Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Block Read Protocol Bit Description 1 Start 8:2 Slave address–7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code– ...

Page 6

... PCI4_OE 3 1 PCI3_OE Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS CPU Frequency Select Bit, set by HW CPU Frequency Select Bit, set by HW CPU Frequency Select Bit, set by HW Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP 0 = Legacy Mode iAMT Enabled, Sticky 1 ...

Page 7

... OE#_1/4_EN_B 0 0 OE#_1/4_SEL_B Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Description Output enable for PCI2 Output Disabled Output Enabled Output enable for PCI1 Output Disabled Output Enabled Output enable for PCI0 Output Disabled Output Enabled Description Output enable for SRC11 Output Disabled Output Enabled ...

Page 8

... SE2_OE Byte 9 Control Register 9 Bit @Pup Name Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Description Enable OE#_6 (clk req) → SRC6 Enable OE#_8 (clk req) → SRC8 Enable OE#_9 (clk req) → SRC9 Enable OE#_10 (clk req) → SRC10 RESERVED RESERVED ...

Page 9

... RESERVED Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Allows control of PCIF0 with assertion of PCI_STOP Free running PCIF Stopped with PCI_STOP# Trusted mode enable strap status normal overclocking REF drive strength control, See Byte 18 for more setting 0 = Low High Mode select either REF/N or tri-state ...

Page 10

... RESERVED 4 0 SATA_SS_EN 3 1 EN_CFG0_SET 2 1 SE1/SE2_DSC1 1 1 RESERVED 0 1 SW_PCI Byte 14 Control Register 14 Bit @Pup Name Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS PCIF0/ITP_EN AMT_EN CPU2_AMT_EN CPU1_AMT_EN PCI-E_Gen2 Compliant 0 = non Gen2, 1= Gen2 Compliant Allow control of CPU2 with assertion of CPU_STOP Free running Stopped with CPU_STOP# ...

Page 11

... RESERVED 0 0 RESERVED Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[C:A] register will be used ...

Page 12

... While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Cs1 Figure 2. Crystal Loading Example SPL505YC256BT/ SPL505YC256BS Description DSC_0 Buf f er DSC_1 ...

Page 13

... When PS is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held LOW. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 µs after asserting CK_PWRGD. SPL505YC256BT/ SPL505YC256BS pin functions as CK_PWRGD. ...

Page 14

... SMBus configuration to be stoppable via assertion of CPU_STP# are stopped within two to six CPU clock periods after being sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. SPL505YC256BT/ SPL505YC256BS Page ...

Page 15

... CPU clock cycles. CPU_STP# CPUT CPUC CPUT Internal CPUC Internal CPU_STP# Deassertion Waveform CPU_STOP# PD# CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven Rev 1.4 March 21, 2007 Tdrive_CPU_STP#,10 ns>200 mV SPL505YC256BT/ SPL505YC256BS 1.8mS Page ...

Page 16

... PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transi- tions to a HIGH level. PCI_STP# PCI_F PCI SRC 100MHz Rev 1.4 March 21, 2007 T su Figure 5. PCI_STP# Assertion Waveform Tdrive_SRC Tsu Figure 6. PCI_STP# Deassertion Waveform SPL505YC256BT/ SPL505YC256BS 1.8mS Page ...

Page 17

... Clock# Driven Low Running Running All Differential Clocks except CPU1 Clock Clock# Low or 20K pulldown Low Low or 20K pulldown Low Low or 20K pulldown Low SPL505YC256BT/ SPL505YC256BS SMBus OE Disabled Driven Low Driven Low or 20K pulldown CPU1 Clock Clock# Low or 20K pulldown Low ...

Page 18

... Figure 8. Clock Generator Power-up/Run State Diagram Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Page ...

Page 19

... OUT L Pin Inductance IN V Xin High Voltage XIH V Xin Low Voltage XIL I Dynamic Supply Current DD3.3V Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Condition Relative Non-functional Functional Functional Mil-STD-883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition 3.3 ± 5% SDATA, SCLK SDATA, SCLK Typ ...

Page 20

... T CPU2_ITP to CPU0 Clock Skew SKEW2 T CPU2_ITP to CPU0 Clock Skew SKEW2 Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0 ...

Page 21

... Rise/Fall Matching RFM V Voltage High HIGH V Voltage Low LOW Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Condition Measured differentially from ±150 mV Measured single-endedly from ±75 mV Measured at 0V differential Measured at 0V differential @ 0.1s Measured at 0V differential @ 0.1s 10.02406 10.02607 Measured at 0V differential @ 1 clock ...

Page 22

... REF Rising and Falling Edge Rate REF Clock to REF Clock SKEW T REF Cycle to Cycle Jitter CCJ Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Condition Measurement at 1.5V Measurement at 1.5V 29.99100 30.00900 Measurement at 1.5V 30.08421 30.23459 Measurement at 1.5V 29.49700 30.50300 Measurement at 1.5V 29.56617 30.58421 Measurement at 2 ...

Page 23

... L 22Ω 50Ω 0.5" 8" 50Ω 22Ω 15Ω 50Ω 15Ω 50Ω 15Ω 50Ω SPL505YC256BT/ SPL505YC256BS Min. Max. Unit – 100 ppm – 1.8 10.0 – Measurement Point 4 pF Measurement Point 4 pF Measurement Point 4 pF Measurement Point 4 pF Measurement Point 4 pF Page ...

Page 24

... Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.4, March 21, 2007 33Ω 50Ω 0.5" 7" 33Ω 50Ω Figure 12. 0.7V Differential Load Configuration SPL505YC256BT/ SPL505YC256BS Measurement Point 2 pF Measurement Point 2 pF Page ...

Page 25

... SPL505YC256BTT 56-pin TSSOP–Tape and Reel SPL505YC256BS 56-pin SSOP SPL505YC256BST 56-pin SSOP–Tape and Reel Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Package Type Product Flow Commercial, 0° to 85°C Commercial, 0° to 85°C Commercial, 0° to 85°C Commercial, 0° to 85°C ...

Page 26

... Package Diagram 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 Rev 1.4 March 21, 2007 56-Lead Shrunk Small Outline Package O56 SPL505YC256BT/ SPL505YC256BS Page ...

Page 27

... Document History Page Document Title: SPL505YC256BT/ Orig. of REV. Issue Date Change 1.0 12/13/06 JMA New data sheet 1.1 1/30/07 JMA 1. Added SE1/SE2 to pinout in pinout diagram 2. Added clarifications to Byte 11 3. Added new definitions to Byte 13 4. Added PCI3/CFG0 voltage requirements in DC parameters 1.2 ...

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