SPL505YC256BTT Silicon Laboratories Inc, SPL505YC256BTT Datasheet

no-image

SPL505YC256BTT

Manufacturer Part Number
SPL505YC256BTT
Description
Clock Generators & Support Products CK505 v0.85
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SPL505YC256BTT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SPL505YC256BTT
Manufacturer:
SPECTRALI
Quantity:
18 150
Rev 1.4 March 21, 2007
2200 Laurelwood Road, Santa Clara, CA 95054
Features
Block Diagram
• Compliant to Intel
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz Differential SRC clocks
• 100 MHz Differential LCD clock
• 96 MHz Differential Dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• 25 MHz WOL or PATA clock
• 27 MHz non-spread Video Clock
®
CK505
Clock Generator for Intel
Tel:(408) 855-0555
Table 1. Output Configuration Table
Pin Configuration
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select input
• I
• Triangular Spread Spectrum profile for maximum
• 3.3V Power supply/0.7V for Diff IOs
• 56-pin TSSOP and SSOP package
x2/x3
CPU
SRC1# / LCD_100#/SE2
electromagnetic interference (EMI) reduction
SRC1 / LCD_100/SE1
2
SRC3# / OE#_1/4_B
C support with readback capabilities
PCI_0 / OE#_0/2_A
PCI_1 / OE#_1/4_A
SRC3/OE#_0/2_B
PCI_4 / SRC5_EN
SRC0# / DOT96#
PCIF_0 / ITP_EN
Fax:(408) 855-0550
SRC2# / SATA#
SRC0 / DOT96
VDD_PLL3_IO
PCI_3 / CFG0*
USB_48 / FSA
VDD_SRC_IO
SRC2 / SATA
PCI_2 / TME
VDD_PLL3
VSS_PLL3
VSS_SRC
x8/12
VDD_PCI
VSS_PCI
SRC
VDD_48
VSS_48
VDD_IO
VSS_IO
SRC4#
SRC4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SPL505YC256BT/
PCI REF DOT96 USB_48M
x6
SPL505YC256BS
* Internal Pull-Down
®
x 1
Bearlake Chipset
www.SpectraLinear.com
x 1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SCLK
SDATA
REF0 / FSC / TEST_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FSB / TEST_MODE
CK_PW RGD / PW RDW N#
VDD_CPU
CPU0
CPU0#
VSS_CPU
CPU1
CPU1#
VDD_CPU_IO
IO_VOUT
SRC8 / CPU2_ITPT
SRC8# / CPU2_ITPC
VDD_SRC_IO
SRC7 / OE#_8
SRC7# / OE#_6
VSS_SRC
SRC6
SRC6#
VDD_SRC
SRC5 / PCI_STOP#
SRC5# / CPU_STOP#
Page 1 of 27
x 1
LCD
x1

Related parts for SPL505YC256BTT

SPL505YC256BTT Summary of contents

Page 1

Features ® • Compliant to Intel CK505 • Selectable CPU frequencies • Differential CPU clock pairs • 100 MHz Differential SRC clocks • 100 MHz Differential LCD clock • 96 MHz Differential Dot clock • 48 MHz USB clocks • ...

Page 2

Pin Definitions Pin No. Name 1 PCI_0/OE#_0/2_A 2 VDD_PCI 3 PCI_1/OE#_1/4_A 4 PCI_2/TME 5 PCI_3/CFG0 6 PCI_4/SRC5_SEL 7 PCIF_0/ITP_EN 8 VSS_PCI 9 VDD_48 10 USB_48/FSA 11 VSS_48 12 VDD_IO 13 SRC0/DOT96 14 SRC0#/DOT96# 15 VSS_IO 16 VDD_PLL3 17 SRC1/LCD_100/SE1 18 ...

Page 3

Pin Definitions (continued) Pin No. Name 30 SRC5/CPU_STOP# 31 VDD_SRC 32 SRC6# 33 SRC6 34 VSS_SRC 35 SRC7#/OE#_6 36 SRC7/OE#_8 37 VDD_SRC_IO 38 SRC8#/CPUT2_ITP# 39 SRC8/CPUC2_ITP 40 IO_VOUT 41 VDD_CPU_IO 42 CPU1# 43 CPU1 44 VSS_CPU 45 CPU0# 46 CPU0 ...

Page 4

Frequency Select Pin (FSA, FSB, and FSC) To achieve host clock frequency selection, apply the appro- priate logic levels to FS_A, FS_B, and FS_C, inputs before CK_PWRGD assertion (as seen by the clock synthesizer). When CK_PWRGD is sampled HIGH by ...

Page 5

Table 3. Block Read and Block Write Protocol Block Write Protocol Bit Description 1 Start 8:2 Slave address–7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code–8 bits 19 Acknowledge from slave 27:20 Byte Count–8 bits 2 (Skip this ...

Page 6

Byte 0: Control Register FS_C 6 HW FS_B 5 HW FS_A 4 0 iAMT_EN 3 0 RESERVED 2 0 SRC_MAIN_SEL 1 0 SATA_SEL 0 1 PD_Restore Byte 1: Control Register 1 Bit @Pup Name 7 0 SRC0_SEL ...

Page 7

Byte 2: Control Register 2 (continued) Bit @Pup Name 2 1 PCI2_OE 1 1 PCI1_OE 0 1 PCI0_OE Byte 3: Control Register 3 Bit @Pup Name 7 1 SRC11_OE 6 1 SRC10_OE 5 1 SRC9_OE 4 1 SRC8/ITP_OE 3 1 ...

Page 8

Byte 6: Control Register 6 Bit @Pup Name 7 0 OE#_6_EN 6 0 OE#_8_EN 5 0 OE#_9_EN 4 0 OE#_10_EN 3 0 RESERVED 2 0 RESERVED 1 0 LCD_100_STP_CTRL 0 0 SRC_STP_CTRL Byte 7: Vendor ID Bit @Pup Name 7 ...

Page 9

Byte 9 Control Register PCIF0_STP_CTRL 6 HW_Pin TME_STRAP 5 1 REF_DSC1 4 0 TEST_MODE_SEL 3 0 TEST_MODE_ENTRY 2 1 IO_VOUT2 1 0 IO_VOUT1 0 1 IO_VOUT0 Byte 10 Control Register 10 Bit @Pup Name 7 HW SRC5_EN_STRAP ...

Page 10

Byte 11 Control Register CPU2_AMT_EN 2 1 CPU1_AMT_EN 1 HW PCI-E_GEN2 0 1 CPU2_STP_CRTL Byte 12 Byte Count Bit @Pup Name 7 0 RESERVED 6 0 RESERVED 5 0 BC5 4 0 BC4 3 1 BC3 2 ...

Page 11

Byte 14 Control Register CPU_DAF_N7 6 0 CPU_DAF_N6 5 0 CPU_DAF_N5 4 0 CPU_DAF_N4 3 0 CPU_DAF_N3 2 0 CPU_DAF_N2 1 0 CPU_DAF_N1 0 0 CPU_DAF_N0 Byte 15 Control Register 15 Bit @Pup Name 7 0 CPU_DAF_N8 ...

Page 12

Byte 18 Control Register 18 Bit @Pup Name 7 0 PCI_DSC2 6 1 PCI_DSC0 5 0 USB_DSC2 4 0 USB_DSC0 3 0 SE1/SE2_DSC2 2 0 SE1/SE2_DSC0 1 0 REF_DSC2 0 0 REF_DSC0 Table 5. Crystal Recommendations Frequency (Fund) Cut Loading ...

Page 13

Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side – (Cs + Ci) Total Capacitance (as seen by the crystal CLe ...

Page 14

PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF PD# Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD# pin or the ...

Page 15

Figure 4. CPU_STP# Assertion Waveform CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation ...

Page 16

CPU_STOP# PD# CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion The PCI_STP# signal is an active LOW input used to synchro- nously stop and start the PCI outputs while ...

Page 17

Table 6. Output Driver Status during PCI-STOP# and CPU-STOP# Single-ended Clocks Stoppable Non Stoppable Differential Clocks Stoppable Non Stoppable Table 7. Output Driver Status All Single-ended Clocks w/o Strap w/Strap Latches Open State Low Hi-Z Powerdown Low Hi-Z M1 ...

Page 18

Figure 8. Clock Generator Power-up/Run State Diagram Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Page ...

Page 19

Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V IO Supply Voltage DD_IO V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction ...

Page 20

AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD T /T XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V T CPUT ...

Page 21

AC Electrical Specifications (continued) Parameter Description T /T CPUT and CPUC Rise and Fall Time Rise/Fall Matching RFM V Voltage High HIGH V Voltage Low LOW V Crossing Point Voltage at 0.7V Swing OX SRC T SRCT ...

Page 22

AC Electrical Specifications (continued) Parameter Description V Crossing Point Voltage at 0.7V Swing OX PCI/PCIF T PCI Duty Cycle DC T Spread Disabled PCIF/PCI Period PERIOD T Spread Enabled PCIF/PCI Period, SSC PERIODSS T Spread Disabled PCIF/PCI Period PERIODAbs T ...

Page 23

AC Electrical Specifications (continued) Parameter Description L Long Term Accuracy ACC ENABLE/DISABLE and SET-UP T Clock Stabilization from Power-up STABLE T Stopclock Set-up Time SS Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows the ...

Page 24

For CPU, SRC, and DOT96 Signals and Reference The following diagram shows the test load configuration for the differential CPU and SRC outputs. OUT+ OUT- Figure 13. Differential Measurement for Differential Output Signals (for AC Parameters Measuremement Figure 14. Single-ended ...

Page 25

... Ordering Information Part Number Lead-free SPL505YC256BT 56-pin TSSOP SPL505YC256BTT 56-pin TSSOP–Tape and Reel SPL505YC256BS 56-pin SSOP SPL505YC256BST 56-pin SSOP–Tape and Reel Rev 1.4 March 21, 2007 SPL505YC256BT/ SPL505YC256BS Package Type Product Flow Commercial, 0° to 85°C Commercial, 0° to 85°C Commercial, 0° ...

Page 26

Package Diagram 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 Rev 1.4 March 21, 2007 56-Lead Shrunk Small Outline Package O56 SPL505YC256BT/ SPL505YC256BS Page ...

Page 27

Document History Page Document Title: SPL505YC256BT/ Orig. of REV. Issue Date Change 1.0 12/13/06 JMA New data sheet 1.1 1/30/07 JMA 1. Added SE1/SE2 to pinout in pinout diagram 2. Added clarifications to Byte 11 3. Added new definitions to ...

Related keywords