SPL505YC256BTT Silicon Laboratories Inc, SPL505YC256BTT Datasheet - Page 10

• Manufacturer Part Number: SPL505YC256BTT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC256BTT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
Byte 11 Control Register 11
Byte 12 Byte Count
Byte 13 Control Register 13
Byte 14 Control Register 14
Bit
Bit
Bit
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
HW
0
1
1
0
0
0
0
1
1
0
1
1
1
0
0
1
1
1
1
CPU2_STP_CRTL
PCI/PCIF_DSC1
CPU2_AMT_EN
CPU1_AMT_EN
SE1/SE2_DSC1
EN_CFG0_SET
SATA_SS_EN
PCI-E_GEN2
RESERVED
RESERVED
RESERVED
RESERVED
USB_DSC1
SW_PCI
Name
Name
Name
BC5
BC4
BC3
BC2
BC1
BC0
PCI-E_Gen2 Compliant
0 = non Gen2, 1= Gen2 Compliant
Allow control of CPU2 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
RESERVED
RESERVED
Byte count
Byte count
Byte count
Byte count
Byte count
Byte count
USB drive strength control, See Byte 18 for more setting
0 = Low, 1= High
PCI drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
RESERVED
Enable SATA spread modulation,
0 = Spread Disabled 1 = Spread Enabled
By defalult CFG0 pin strap sets the SMBus initial values to select the HW
mode. When this bit is written0, subsequent SMBus accesses is the Lathes
Open state, can overwrite the CFG0 pin setting into the SMBus bits and set
the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5
SE1 and SE2 drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
RESERVED
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
PCIF0/ITP_EN
x
x
1
1
AMT_EN
1
1
1
1
CPU2_AMT_EN
0
0
1
1
Description
Description
Description
CPU1_AMT_EN
SPL505YC256BT/
SPL505YC256BS
0
1
0
1
Page 10 of 27
Reserved
CPU1 = M1 Clock
CPU2 - M1 Clock
CPU1 and CPU2 = M1 Clock
Description