SPL505YC256BTT Silicon Laboratories Inc, SPL505YC256BTT Datasheet - Page 17

• Manufacturer Part Number: SPL505YC256BTT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC256BTT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
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Table 6. Output Driver Status during PCI-STOP# and CPU-STOP#
Table 7. Output Driver Status
PD_RESTORE
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#
LOW, the CY505 will initiate a full reset. The results of this will
be that the clock chip will emulate a cold power on start and
go to the ‘Latches Open’ state. If the PD_RESTORE bit is set
to a ‘1’ then the configuration is stored upon PWRDWN#
asserted LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to
a ‘1’ then the PD_RESTORE bit must be ignored. In other
words, in Intel iAMT mode, PWRDWN# reset is not allowed.
Single-ended Clocks Stoppable
Differential Clocks
Latches Open State Low
Powerdown
M1
Non Stoppable
Stoppable
Non Stoppable
w/o Strap
Low
Low
All Single-ended Clocks
w/Strap
Hi-Z
Hi-Z
Hi-Z
Driven Low
Running
Clock Drive High
Clock# Driven Low
Running
PCI_STOP# Asserted
Figure 7. CK_PWRGD Timing Diagram
Clock
Low or 20K pulldown Low
Low or 20K pulldown Low
Low or 20K pulldown Low
All Differential Clocks except
CPU1
Running
Running
Running
Clock Drive High
Clock# Driven Low
CPU_STOP# Asserted
Clock#
Clock
Low or 20K pulldown Low
Low or 20K pulldown Low
Running
SPL505YC256BT/
SPL505YC256BS
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Driven Low
Driven Low or 20K
pulldown
SMBus OE Disabled
CPU1
Clock#
Running