MC100EP196FA ON Semiconductor, MC100EP196FA Datasheet

Delay Lines / Timing Elements 3.3V/5V ECL

MC100EP196FA

Manufacturer Part Number

MC100EP196FA

Description

Delay Lines / Timing Elements 3.3V/5V ECL

Manufacturer

ON Semiconductor

Datasheet

1.MC100EP196FA.pdf (18 pages)

Specifications of MC100EP196FA

Function

Active Programmable Delay Line

Supply Voltage (min)

+/- 3 V

Maximum Operating Temperature

+ 85 C

Minimum Operating Temperature

- 40 C

Mounting Style

SMD/SMT

Supply Voltage (max)

+/- 3.6 V

Package / Case

LQFP-32

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Download datasheet (191Kb)

MC100EP196

3.3V ECL Programmable

Delay Chip with FTUNE

primarily for clock deskewing and timing adjustment. It provides variable

delay of a differential NECL/PECL input transition. It has similar

architecture to the EP195 with the added feature of further tuneability in

delay using the FTUNE pin. The FTUNE input takes an analog voltage

from V

multiplexers as shown in the logic diagram, Figure 2. The delay increment

of the EP196 has a digitally selectable resolution of about 10 ps and a net

range of up to 10.2 ns. The required delay is selected by the 10 data select

inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on

LEN allows a transparent LOAD mode of real time delay values by

D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD

current values present against any subsequent changes in D[10:0]. The

approximate delay values for varying tap numbers correlating to D0 (LSB)

through D9 (MSB) are shown in Table 5.

fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for

controlling Pins 14 and 15, CASCADE and CASCADE, also latched

by LEN, in cascading multiple PDCs for increased programmable

range. The cascade logic allows full control of multiple PDCs.

Switching devices from all “1” states on D[0:9] with SETMAX LOW

to all “0” states on D[0:9] with SETMAX HIGH will increase the

delay equivalent to “D0”, the minimum increment.

combinations of interconnects between V

for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS

operation is available in PECL mode only. For LVCMOS input levels,

leave V

(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply

reference to V

to V

this device only. For single−ended input conditions, the unused

differential input is connected to V

and V

to 0.5 mA. When not used, V

•

August, 2010 − Rev. 15

The MC100EP196 is a programmable delay chip (PDC) designed

The delay section consists of a programmable matrix of gates and

Because the EP196 is designed using a chain of multiplexers, it has a

Select input pins, D[10:0], may be threshold controlled by

The V

The 100 Series contains temperature compensation.

Maximum Frequency > 1.2 GHz Typical

Programmable Range: 0 ns to 10 ns

Delay Range: 2.4 ns to 12.4 ns

10 ps Increments

PECL Mode Operating Range:

NECL Mode Operating Range:

and V

may also rebias AC coupled inputs. When used, decouple V

pin can be accomplished by placing a 2.2 kW resistor between

= 3.0 V to 3.6 V with V

= 0 V with V

via a 0.01 mF capacitor and limit current sourcing or sinking

to V

and V

pin, an internally generated voltage supply, is available to

for 3.3 V power supply.

and leave open V

to fine tune the output delay from 0 to 60 ps.

open. For ECL operation, short V

= −3.0 V to −3.6 V

should be left open.

= 0 V

pin. The 1.5 V reference voltage

as a switching reference voltage.

(pin 7) and V

and V

(pin 8)

•

Open Input Default State

Safety Clamp on Inputs

A Logic High on the EN Pin Will Force Q to Logic

Low

D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL

Inputs

Pb−Free Packages are Available*

Output Reference Voltage

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

*For additional information on our Pb−Free strategy

and soldering details, please download the

ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

*For additional marking information, refer to

Application Note AND8002/D.

CASE 873A

FA SUFFIX

LQFP−32

ORDERING INFORMATION

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Publication Order Number:

DIAGRAM*

AWLYYWWG

MARKING

MC100EP196/D

MC100

EP196

Related parts for MC100EP196FA

MC100EP196FA Summary of contents

Page 1

... ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Publication Order Number: MC100EP196/D ...

Page 2

MC100EP196 D10 ...

Page 3

Table 1. PIN DESCRIPTION Pin Name I/O 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, 29, 30, 31, 32, ECL Input D[10] LVCMOS, LVTTL, ECL Input 4 IN ECL Input 5 IN ECL Input 6 V − BB ...

Page 4

Table 2. CONTROL PIN Pin State EN LOW (Note 3) HIGH LEN LOW (Note 3) HIGH SETMIN LOW (Note 3) HIGH SETMAX LOW (Note 3) HIGH D10 LOW HIGH 3. Internal pulldown resistor will provide a logic LOW if pin ...

Page 5

Figure 2. Logic Diagram http://onsemi.com 5 ...

Page 6

Table 5. THEORETICAL DELTA DELAY VALUES D(9:0) Value XXXXXXXXXX 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 XXXXXXXXXX *Fixed minimum delay not included. Table 6. TYPICAL FTUNE DELAY PIN Input Range V ...

Page 7

Figure 3. Measured Delay vs. Select Inputs Table 7. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture ...

Page 8

Table 8. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

Page 9

Table 9. DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 10

Table 10. DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 11

Table 11. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency max t Propagation Delay PLH D(0− PHL D(0−9) = 1023 D(0− D10 to CASCADE t Programmable ...

Page 12

Using the FTUNE Analog Input The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable gate to enhance the 10 ps resolution capabilities of the fully digital EP196. The level of resolution obtained ...

Page 13

Cascading Multiple EP196s To increase the programmable range of the EP196, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP196s without the need for any external gating. Furthermore, this capability requires only one more ...

Page 14

An expansion of the latch section of the block diagram is pictured in Figure 7. Use of this diagram will simplify the explanation of how the SETMIN and SETMAX circuitry works in cascade. When D10 of chip #1 in Figure ...

Page 15

Table 12. CASCADED DELAY VALUE OF TWO EP196S VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 ...

Page 16

Multi−Channel Deskewing The most practical application for EP196 is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To deskew multiple signal channels, each channel can be sent ...

Page 17

... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP196FA MC100EP196FAG MC100EP196FAR2 MC100EP196FAR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 18

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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