Timers & Support Products LOG CMOS OSILATR TIMER

MC14541BCP

Manufacturer Part NumberMC14541BCP
DescriptionTimers & Support Products LOG CMOS OSILATR TIMER
ManufacturerON Semiconductor
TypeProgrammable
MC14541BCP datasheet
 

Specifications of MC14541BCP

Number Of Internal Timers1Supply Voltage (max)18 V
Supply Voltage (min)3 VMaximum Power Dissipation500 mW
Maximum Operating Temperature+ 125 CMinimum Operating Temperature- 55 C
Mounting StyleThrough HolePropagation Delay (max)18000 ns, 10000 ns, 7500 ns
Package / CasePDIP-14Lead Free Status / RoHS StatusLead free / RoHS Compliant
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TYPICAL RC OSCILLATOR CHARACTERISTICS
8.0
V
4.0
0
10 V
- 4.0
- 8.0
5.0 V
- 12
R
= 56 kW,
R
= 0, f = 10.15 kHz @ V
TC
S
R
= 120 kW, f = 7.8 kHz @ V
C = 1000 pF
S
- 16
- 55
- 25
0
25
50
T
, AMBIENT TEMPERATURE (°C)
A
Figure 4. RC Oscillator Stability
With Auto Reset pin set to a “0” the counter circuit is
initialized by turning on power. Or with power already on,
the counter circuit is reset when the Master Reset pin is set
to a “1”. Both types of reset will result in synchronously
resetting all counter stages independent of counter state.
Auto Reset pin when set to a “1” provides a low power
operation.
The RC oscillator as shown in Figure 3 will oscillate with
a frequency determined by the external RC network i.e.,
1
f =
if (1 kHz v f v 100 kHz)
2.3 R
C
tc
tc
and R
≈ 2 R
where R
≥ 10 kW
S
tc
S
The time select inputs (A and B) provide a two−bit address
to output any one of four counter stages (2
16
n
2
). The 2
counts as shown in the Frequency Selection
Table represents the Q output of the N
16
When A is “1”, 2
is selected for both states of B. However,
R
tc
1
C
tc
2
3
R
S
4
NC
AR
5
MR
6
INPUT
7
t
MR
100
= 15 V
50
DD
20
10
5.0
f AS A FUNCTION
2.0
(R
TC
1.0
(R
S
0.5
0.2
= 10 V, T
= 25°C
DD
A
= 10 V, T
= 25°C
DD
A
0.1
75
100
125
1.0 k
0.0001
OPERATING CHARACTERISTICS
when B is “0”, normal counting is interrupted and the 9th
counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 2
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a “0” the Q output is a “0”,
correspondingly when Q/Q select pin is set to a “1” the Q
output is a “1”.
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the R
Expanded Block Diagram) resets, counting commences,
and after 2
output to change state. Hence, after another 2
8
10
13
, 2
, 2
and
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
th
stage of the counter.
the single cycle operation.
DIGITAL TIMER APPLICATION
When Master Reset (MR) receives a positive pulse, the
internal counters and latch are reset. The Q output goes high
V
14
DD
and remains high until the selected (via A and B) number of
13
B
clock pulses are counted, the Q output then goes low and
12
A
remains low until another input pulse is received.
11
N.C.
This “one shot” is fully retriggerable and as accurate as the
MODE
10
input frequency. An external clock can be used (pin 3 is the
Q/Q
9
V
DD
clock input, pins 1 and 2 are outputs) if additional accuracy
8
is needed.
OUTPUT
Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up,
during which time Q output will be high.
t + t
MR
http://onsemi.com
6
V
= 10 V
DD
f AS A FUNCTION
OF R
(C = 1000 pF)
≈ 2R
(R
S
OF C
= 56 kW)
= 120 kW)
10 k
100 k
R
, RESISTANCE (OHMS)
TC
0.001
0.01
C, CAPACITANCE (mF)
Figure 5. RC Oscillator Frequency as a
Function of R
and C
tc
tc
8
).
flip−flop (see
S
n−1
counts the R
flip−flop sets which causes the
S
n−1
TC
)
TC
1.0 m
0.1
counts the