LAN91C110-PU SMSC, LAN91C110-PU Datasheet
LAN91C110-PU
Specifications of LAN91C110-PU
Available stocks
Related parts for LAN91C110-PU
LAN91C110-PU Summary of contents
Page 1
... Adaptable to ISA, PCMCIA (16-bit CardBus), and Various CPU System Interfaces Support for 16 and 8 Bit CPU Accesses Asynchronous Bus Interface 128 Kbyte External Memory LAN91C110-PU for 144 pin TQFP lead-free RoHS Compliant package SMSC LAN91C110 Rev. B LAN91C110 REV. B FEAST Fast Ethernet Controller for ...
Page 2
... OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 2 ...
Page 3
... Figure 2.1 – Pin Configuration ...................................................................................................................... 6 Figure 3.1 - LAN91C110 Block Diagram..................................................................................................... 10 Figure 3.2 - LAN91C110 System Diagram ................................................................................................. 10 Figure 4.1 - LAN91C110 Internal Block Diagram with Data Path ............................................................... 14 Figure 5.1 – Data Packet Format................................................................................................................ 15 Figure 5.2 – Interrupt Structure................................................................................................................... 33 Figure 5.3 – Interrupt Service Routine ........................................................................................................ 41 Figure 5 ...
Page 4
... Figure 7.5 - MII Interface............................................................................................................................. 55 Figure 8.1 - 144 Pin TQFP Package Outlines............................................................................................. 56 List of Tables Table 5.1 - Internal I/O Space Mapping........................................................................................................ 18 Table 8.1 – 144 Pin TQFP Package Parameters ....................................................................................... 56 SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 4 DATASHEET Datasheet ...
Page 5
... CPU to packet RAM data movement does not cause a bottleneck at 100 Mbps. The LAN91C110 implements a generic 16-bit host interface which is adaptable to a wide range of system buses and CPUs. This makes the LAN91C110 ideal for 10/100 Fast Ethernet implementations in systems based on system buses other than PCI ...
Page 6
... RD4 28 GND 29 RD3 30 RD2 31 RD1 32 VDD 33 RD0 34 RD15 35 RD14 36 SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications LAN91C110 144 Pin TQFP Figure 2.1 – Pin Configuration Page 6 DATASHEET Datasheet 108 A9 A8 107 A7 106 A6 105 104 A5 A4 ...
Page 7
... IS Input. Address strobe. For systems that require address latching. The rising edge of nADS indicates the latching moment of A[1:15] and AEN. All LAN91C110 internal functions of A[1:15] and AEN are latched. O4 Output. The interrupt output is enabled by selecting the appropriate routing bits (INT SEL the Configuration Register ...
Page 8
... Reads are always 32 bits wide. Writes are controlled individually at the byte level. O4 Outputs. This bus specifies the buffer RAM doubleword being accessed by the LAN91C110. O4 Output. Active low signal used to read a doubleword from buffer RAM. O4 Outputs. Active low signals used to write any byte, word or dword in RAM ...
Page 9
... BUFFER TYPE I with Input. Indicates a code error detected by PHY. pulldown Used by the LAN91C110 to discard the packet being received. The error indication reported for this event is the same as a bad CRC (Receive Status Word bit 13). O4 Output. Chip Select provided for mapping of PHY functions into LAN91C110 decoded space. Active on accesses to LAN91C110’ ...
Page 10
... DIRECT MEMORY ACCESS MEMORY MANAGEMENT UNIT RAM 25 MHz Figure 3.1 - LAN91C110 Block Diagram LAN91C110 FEAST MII OE,WE RD0- Figure 3.2 - LAN91C110 System Diagram Page 10 DATASHEET Datasheet 10/100 Mb/s Media MEDIA Independent Interface ACCESS CONTROL 100BASE-T4 INTERFACE CHIP 100BASE-T4 100BASE-TX 100BASE-TX/ INTERFACE ...
Page 11
... The Arbiter is also responsible for controlling the nRWE0-nRWE3 lines as a function of the bytes being written. Read accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to the appropriate lanes as a function of the address. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 11 ...
Page 12
... With ISA, the read and write operations are controlled by the edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle. The leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C110 clock and, therefore, asynchronous to the bus. ...
Page 13
... The MII SELECT bit in the CONFIG REGISTER must always be set for proper chip function. Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running clocks. The LAN91C110 will not rely on the presence of TX25 and RX25 during reset and will use its own internal clock whenever a timeout on TX25 is detected. ...
Page 14
... Bus Interface Address Control Unit WR FIFO Data RD FIFO Figure 4.1 - LAN91C110 Internal Block Diagram with Data Path SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Control Control Control Arbiter MMU TX/RX DMA FIFO Pointer ...
Page 15
... BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications 2nd Byte ...
Page 16
... On transmit, all bytes are provided by the CPU, including the source address. The LAN91C110 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C110 treated transparently as data both for transmit and receive operations. ...
Page 17
... The odd byte can be accessed using address (offset + 1). Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications HASH VALUE 5-0 ...
Page 18
... BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the register bank in use. The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C110. The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2. ...
Page 19
... FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the LAN91C110 will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted ...
Page 20
... LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit frame. MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced. Cleared when TX_SUC is high at the end of the packet being sent. SMSC LAN91C110 Rev. B NAME TYPE READ ONLY ...
Page 21
... SOFT_RST - Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C110’s configuration is not preserved except for Configuration, Base, and IA0-IA5 Registers. EEPROM is not reloaded after software reset. FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). Otherwise recognizes a receive frame as soon as carrier sense is active ...
Page 22
... MEMORY SIZE - This register can be read to determine the total memory size. All memory related information is represented in 256 * M byte units, where the multiplier M is determined by the MCR upper byte. These register default to FFh, which should be interpreted as 256. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE ...
Page 23
... The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the Memory Size Multiplier. M=2 for the LAN91C110. A value of 04h in the lower byte of the MCR is equal to one 2K page (4 * 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only when the entire memory is being reserved for transmit (i ...
Page 24
... MII SELECT - Used to select the network interface port. When set, the LAN91C110 will use its MII port and interface a PHY device at the nibble rate. This bit must always be set for proper chip function. NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not ready for a transfer ...
Page 25
... HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 BANK 1 OFFSET NAME A Reserved. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE READ/WRITE ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS 5 ...
Page 26
... TE ENABLE bit. TE ENABLE defaults low (disabled). Transmit Error is any condition that clears TXENA with TX_SUC staying low as described in the EPHSR register. Reserved 2-0: These reserved bits must always be written to as zero(0). SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TYPE ...
Page 27
... Namely N2, N1 will request 2 * 256 = 512 bytes. A shift-based divide by 256 of the packet length yields the appropriate value to be used as N2, N1, N0. Immediately generates a completion code at the ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion. N2, N1, N0 are ignored by the LAN91C110 but should be implemented in LAN91C110 software drivers for LAN9000 compatibility. 010 ...
Page 28
... Note 1: Bits N2,N1,N0 bits are ignored by the LAN91C110 but should be used for command 0 to preserve software compatibility with the LAN91C92 and future devices. They should be zero for all other commands. Note 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them ...
Page 29
... Note: For software compatibility with future versions, the value read from each FIFO register is intended to be written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively). SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
Page 30
... Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value. BANK 2 OFFSET 8 THROUGH Bh DATA REGISTER SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE READ/WRITE NOT EMPTY is a read only bit NOT READ Reserved EMPTY ...
Page 31
... DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register. This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C110 regardless of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre- fetched from memory into the read FIFO ...
Page 32
... RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. Receive Interrupt is cleared when RX FIFO is empty. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Page 32 ...
Page 33
... SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications Figure 5.2 – Interrupt Structure Page 33 DATASHEET Datasheet Revision 1.0 (11-04-08) ...
Page 34
... With the proper memory structure, the search is limited to comparing only the multicast addresses that have the actual hash value in question. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
Page 35
... LOW CHIP BYTE 1 0 CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications NAME TYPE READ/WRITE MDOE ...
Page 36
... RCV DISCRD is self clearing. MBO – Must be 1. BANK7 OFFSET 0 THROUGH 7 EXTERNAL REGISTERS nCSOUT is driven low by the LAN91C110 when a valid access to the EXTERNAL REGISTER range occurs. HIGH BYTE LOW BYTE SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ...
Page 37
... Register. Write the packet number into the Packet Number Register. The corresponding status word is now readable from memory. If status word shows successful transmission, issue RELEASE SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications nCSOUT Driven low. Transparently latched on nADS rising edge ...
Page 38
... SERVICE INTERRUPT – Read Interrupt Status Register, exit the interrupt service routine. b) Option 1) Release the packet. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAC SIDE MAC SIDE The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state ...
Page 39
... Option 2) Check the transmit status in the EPH STATUS Register, write the packet number of the current packet to the Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAC SIDE Page 39 DATASHEET Datasheet Revision 1 ...
Page 40
... CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAC SIDE A packet is received with matching address. ...
Page 41
... Call TX INTR or TXEMPTY INTR Get Next TX Packet Available for Transmission? Yes Call ALLOCATE Call EPH INTR SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ISR Save Bank Select & Address Ptr Registers Mask SMC91C100FD Interrupts Read Interrupt Register No ...
Page 42
... SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes Destination No Multicast? Read Words from RAM for Address Filtering Address Yes No Filtering Pass? Yes No Status Word OK? Do Receive Lookahead ...
Page 43
... SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TX INTR Save Pkt Number Register Read TXDONE Pkt # from FIFO Ports Reg. Write Into Packet Number Register Write Address Pointer Register Read Status Word from RAM Yes TX Status ...
Page 44
... TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) Figure 5.6 - TXEMPTY INTR (Assumes auto release option selected) SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR ...
Page 45
... Write Source Address into Copy Remaining TX Data Set "Ready for Packet" Flag Return Buffers to Upper Layer Figure 5.7 - Drive Send and Allocate Routines SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications ALLOCATE Issue "Allocate Memory" Command to MMU ...
Page 46
... If the value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. Note that with the memory management built into the LAN91C110, the CPU can dynamically program this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory) ...
Page 47
... This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that when AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed successfully. Note : The pointer register is shared by any process accessing the LAN91C110 memory. In order to allow processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt ...
Page 48
... OPTIONS TX INT ALLOC INT 'NOT EMPTY' PACKET NUMBER Figure 5.8 – Interrupt Generation for Transmit, Receive, MMU SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications 'NOT EMPTY' PACKET NUMBER REGISTER 'EMPTY' TX DONE CPU ADDRESS M.S. BIT ONLY ...
Page 49
... CLK Low Input Level High Input Level Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications SYMBOL MIN TYP MAX V 0.8 ILI 2 ...
Page 50
... CAPACITANCE 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance CAPACITIVE LOAD ON OUTPUTS ARDY, D0-D15 240 pF All other outputs 45 pF SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications SYMBOL MIN TYP MAX V 0 -10 +10 ...
Page 51
... Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t8 A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE1 Hold after nADS Rising SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications A1-A15, AEN, nBE0-nBE1 valid D0-D15 valid ...
Page 52
... Figure 7.3 – Address Latching for All Modes PARAMETER t8 A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE1 Hold After nADS Rising t25 A4-A15, AEN to nLDEV Delay SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications t8 t9 A1-A15, AEN, nBE0-nBE1 t25 MIN TYP ...
Page 53
... Read – RD0-RD31 Hold after RA2-RA16 Change t52 Read – nROE enable to RD0-RD31 Valid t53 Read – nROE disable to RD0-RD31 Invalid t50 Read/Write – Cycle Time SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications t50 t50 t54 t35 t38 ...
Page 54
... The following is the list of potential SRAMs and suppliers for the LAN91C110 Rev B. These SRAMs meet all timing requirements for LAN91C110 Rev B. But any other SRAM that meets the specification will also work with the LAN91C110 Rev B. Min ≥ 3ns Max≤15ns Min≤25ns Max≤12ns Max≤8ns Min≤12ns Min≤12ns Min≤15ns ...
Page 55
... TXD0-TXD3, TXEN100 Delay from TX25 Rising t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications t27 t27 Figure 7.5 - MII Interface Page 55 ...
Page 56
... Note 4: Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.78-1.08 mm. Note 5: Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN91C110 Rev. B FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications MAX 1 ...