CS61584A-IL3 Cirrus Logic Inc, CS61584A-IL3 Datasheet
CS61584A-IL3
Specifications of CS61584A-IL3
Related parts for CS61584A-IL3
CS61584A-IL3 Summary of contents
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... ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l TR-NET-00499 Description The CS61584A is a dual line interface for T1/E1 appli- cations, designed for high-volume cards where low power and high density are required. The device is op- timized for flexible microprocessor control through a serial or parallel Host mode interface ...
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... The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com DS261PP5 CS61584A CS61584A DS261PP5 DS261F1 ...
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... Designing for AT&T 62411 ............................................................................................ 51 13.7 Line Protection ............................................................................................................... 51 13.8 Loop Selection Equations .............................................................................................. 51 LIST OF TABLES Table 1. Line Configuration Selections............................................................................................. 17 Table 3. Jitter Attenuation Control.................................................................................................... 19 Table 4. CS61584A Register Set ..................................................................................................... 23 Table 5. Status Registers ................................................................................................................. 24 Table 6. Mask Registers................................................................................................................... 25 Table 7. Control A Registers ............................................................................................................ 26 Table 8. Control B Registers ............................................................................................................ 27 Table 9. Arbitrary Waveform Registers ............................................................................................ 28 Table 10 ...
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... Figure 10. Parallel Port Timing - Intel Read Mode from RAM or ROM ......................................... 13 Figure 11. Parallel Port Timing - Intel Write Mode to RAM ........................................................... 13 Figure 12. JTAG Switching Characteristics ................................................................................... 14 Figure 13. Examples of CS61584A Applications ........................................................................... 15 Figure 14. Typical Pulse Shape at DSX-1 Cross Connect ............................................................ 17 Figure 15. Mask of the Pulse at the 2048 kbps Interface .............................................................. 17 Figure 16 ...
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... (Note 5) (Note 6) - (Note 5) - (Note 5) - 1XCLK = 1 (1.544 - 100 ppm) 1XCLK = 0 (12.352 - 100 ppm) 1XCLK = 1 (2.048 - 100 ppm) 1XCLK = 0 (16.384 - 100 ppm) CS61584A CS61584A Max Unit 6.0 V (RV °C 150 °C Typ Max Unit V 3.3 3.465 5.0 5. °C mW 310 - 190 ...
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... A Symbol (Note 7) (Note 8) 9) (Note 10) (Note 11) (Notes 12, 13, and 14) (Notes 12 and 15) (Notes 12 and 15) (Note 12 and ABS(( where z = impedance of the transmitter or receiver, and CS61584A CS61584A Min Typ Max Unit - -13 0 Peak 160 175 190 bits 300 - - 6 0 ...
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... E1, 75 E1, 120 at the output of the transmit transformer for CON3/2/1/0 = 0/0/0/0. at the output of the transmit transformer for CON3/2/1/0 = 0/0/0/1. resistor during the transmission of 100% ones. CS61584A CS61584A Min Typ Max Unit V 2.14 2.37 2.6 2.7 3 ...
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... Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. For the gapped clock to be tolerated by the CS61584A, the jitter attenuator must be switched to the transmit path of the line interface. The maximum gap size that can be tolerated on TCLK is 28 UIp-p. ...
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... Figure 2. Recovered Clock and Data Switching Characteristics Figure 3. Transmit Clock and Data Switching Characteristics DS261PP5 DS261F1 DS261PP5 t r 90% 10% Figure 1. Signal Rise And Fall Characteristics t pw1 t pwl1 t pwh1 t t su1 h1 t pw2 t pwh2 TCLK t su2 t h2 TPOS TNEG TDATA CS61584A CS61584A t f 90% 10 ...
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... SPOL = DS261PP5 Symbol cdh (Note 28) t cch t cwh (Note 29) t cdv t cdz cdh LSB DATA BYTE Figure 4. Serial Port Write Timing Diagram t cdv Figure 5. Serial Port Read Timing Diagram CS61584A CS61584A ( °C; DV+, TV+, RV Min Typ Max 100 - - - - rising edge of SCLK during ...
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... DS261PP5 DS261PP5 (T A Symbol Min t 250 cyc PW 150 el PW 150 rwh t 50 rws 130 csr dhr t 5 dhw t 15 asl t 10 ahl t 25 asd ased t 20 ddr t 80 dsw t 5 dkd t 5 dkh t 50 aamir CS61584A CS61584A = - °C; Max Unit - 120 ...
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... Figure 6. Parallel Port Timing - Motorola Mode t cyc PW ash t asd t t asd ased asl t ahl t cyc PW ash t asd t t ased asd asl t ahl Figure 8. Parallel Port Timing - Intel Write Mode CS61584A CS61584A cyc t rwh t ddr t dhr dsw t dhw t dkh dhr t ddr dhw t dsw ...
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... PW t aamir t csr t asl t ahl PW t aamir t csr t asl t ahl CS61584A CS61584A cyc t rwh t ddr t dhr dsw t dhw t t dkd dkh t cyc ash t ased ddr t ahl t cyc ash ...
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... Cycle Time J-TMS/J-TDI to J-TCK Rising Setup Time J-TCK Rising to J-TMS/J-TDI Hold Time J-TCK Falling to J-TDO Valid J-TCK J-TMS J-TDI J-TDO 14 14 DS261PP5 ( °C; TV+, RV+ = nominal ± 0 Symbol t cyc cyc Figure 12. JTAG Switching Characteristics CS61584A CS61584A Min Max Unit 200 - DS261PP5 DS261F1 ...
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... OVERVIEW The CS61584A is a dual line interface for T1/E1 applications, designed for high-volume cards where low power and high density are required. The device can be operated in either Hardware mode using control pins or in Host mode using an internal register set. One board design can support ...
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... In 62411 applications, the management of jitter is a very important design consideration. Typically, the jitter attenuator is placed in the receive path of the CS61584A to reduce the jitter input to the system synchronizer. The jitter attenuated recovered clock is used as the input to the transmit clock to imple- ment a loop-timed system. A Stratum 4 (±32 ppm) quality clock or better should be input to REFCLK ...
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... DSX-1: 533-655 ft. Arbitrary DSX-1 Waveform DS1: FCC Part 68 Option A with undershoot DS1: FCC Part 68 Option A (0 dB) Arbitrary DS1 Waveform Tristate TTIP/TRING Driver Outputs Tristate TTIP/TRING Driver Outputs Table 1. Line Configuration Selections CS61584A CS61584A 269 ns 244 ns 194 ns G.703 Specification Nominal Pulse 219 ns 488 ns ...
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... The CS61584A driver will automatically detect an inactive TLCK (i.e., no data clocked to the driver) or REFCLK input. When either of these conditions are detected the driver is forced to the tristate (high- impedance) condition ...
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... SONET and SDH), the jitter attenuator is typically used in the transmit path. The attenuator can accept a transmit clock with gaps 28 UIs and a transmit clock burst rate of ATTEN1 ATTEN0 CS61584A CS61584A 8 MHz. Location of Jitter Attenuator 0 Receiver 1 Disabled 0 Transmitter 1 Receiver w/ 1.25 Hz knee Table 3 ...
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... REFERENCE CLOCK The CS61584A requires a reference clock with a minimum accuracy of ±100 ppm for T1 and E1 ap- plications. This clock can be either a 1X clock (i.e., 1.544 MHz or 2.048 MHz), or can clock (i.e., 12.352 MHz or 16.384 MHz) as selected by the 1XCLK pin. This clock may be supplied from internal system timing or a CMOS crystal oscillator and input to the REFCLK pin ...
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... Receive All Ones During Host mode operation, the data at RPOS and RNEG (or RDATA) may be forced to output an un- framed all-ones pattern by setting both the LLOOP1 and LLOOP2 bits in the Control B regis- ter to "1". An automatic Receive All Ones (AAO) CS61584A CS61584A 21 21 ...
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... During Host mode parallel port op- eration, setting the CON[3:0] bits in the Control B register to "111X" tristates the driver. In host mode, the CS61584A powers up with CON[3:0] set to 1110, which tristates the transmitter. 8.11 Power Down During Hardware mode operation, channel power down is selected by setting the PD1 or PD2 pin high ...
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... Table 4. CS61584A Register Set 9.1.1 Status Registers The Status registers are read-only registers and are shown in Table 5. The CS61584A generates an in- terrupt on the INT pin any time an unmasked Status register bit changes. When BTS is low (Intel mode), the IPOL pin determines the polarity of the INT pin ...
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... Status Register (Channel 2) Definition 1 no LOS no LOS no AIS no AIS no BPV no overflow TCLK and REFCLK present no interrupt Table 5. Status Registers "Short" AIS/LOS event Cleared by read Set by start of AIS/LOS Cleared by read Set by Change of AIS/LOS CS61584A CS61584A Reset Value Reset Value " ...
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... Mask Interrupt Enable Interrupt Mask Interrupt Enable Interrupt Mask Interrupt Enable Interrupt Mask Interrupt Enable Interrupt Mask Interrupt Enable Interrupt Mask Interrupt Enable Interrupt Mask Interrupt Enable Interrupt Mask Interrupt Enable Interrupt Table 6. Mask Registers CS61584A CS61584A Reset Value Reset Value ...
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... Normal operation Control A Register (Channel 2) Definition 1 Excessive zeros detection for both channels disabled Power up channel Jitter attenuator location (See Jitter Attenuator section) Transparent mode enabled B8ZS/HDB3 encoder enabled B8ZS/HDB3 decoder enabled Normal operation Table 7. Control A Registers CS61584A CS61584A Reset Value Reset Value 0 ...
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... Disable local loopback #2 Line configuration selections (See Transmitter section) Control B Register (Channel 2) Definition 1 Disable transmit all ones Disable remote loopback Disable local loopback #1 Disable local loopback #2 Line configuration selections (See Transmitter section) Table 8. Control B Registers CS61584A CS61584A Reset Value Reset Value ...
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... CON[3:0] configuration selection to one of the arbitrary generation settings (i.e., 1001, 1010, or 1011). For DS1 applications, the CS61584A divides the 648 ns UI into 14 equal phases of 46.3 ns. For DSX-1 applications, the 648 divided into 13 equal phases of 49.8 ns. The phase amplitude in- formation written for phase 14 of each UI is ig- nored ...
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... UI to rise or fall more quickly. This is illustrated in Figure 20. If the hexadecimal sum of the phase amplitudes ex- ceeds the full scale values, the sum is replaced by the full scale value and the Latched-Overflow bit is set in the Status register. Figure 20. Example of Summing of Waveforms CS61584A CS61584A 29 29 ...
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... Serial port operation in Host mode is selected when the MODE pin is set high and the P/S pin is set low. In this mode, the CS61584A register set is accessed by setting the chip select (CS) pin low and commu- nicating over the SDI, SDO, and SCLK pins. Tim- ing over the serial port is independent of the transmit and receive system timing ...
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... This verification is supported by the abil- ity to externally set the signals on the digital output pins of the CS61584A, and to externally read the signals present on the input pins of the CS61584A. Additionally, the manufacturer ID, part number and revision of the device can be read during board test using JTAG boundary scan ...
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... Host mode. Device Identification Register: The DIR provides the manufacturer, part number, and version of the CS61584A. This information can be used to verify that the proper version or revision number has been used in the system under test. The DIR is 32 bits long and is partitioned as shown in Table 11. Data from the DIR is shifted out to J-TDO LSB first ...
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... EXTEST connects the BSR to the J- TDI and J-TDO pins. The normal path between the CS61584A logic and I/O pins is broken. The sig- nals on the output pins are loaded from the BSR and the signals on the input pins are loaded into the BSR ...
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... Select-DR-Scan 0 1 Capture-DR 0 Shift- Exit1-DR 0 Pause- Exit2-DR 1 Update- Figure 24. TAP Controller State Diagram CS61584A CS61584A 1 Select-IR-Scan 0 1 Capture-IR 0 Shift- Exit1-IR 0 Pause- Exit2-IR 1 Update- DS261PP5 DS261F1 ...
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... When the controller is in this state and a rising edge is applied to J-TCK, the controller enters the Exit1-IR state if J-TMS is held high, or remains in the Shift-IR state if J-TMS is held low. CS61584A CS61584A 35 35 ...
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... The test data registers selected by the current instruction retain their previous val- ue. 10.20 JTAG Application Examples Figures 25 and 26 illustrate examples of updating the instruction and data registers during JTAG op- eration. CS61584A CS61584A DS261PP5 DS261F1 ...
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... Parallel output of IR Parallel Input to TDR Parallel output of TDR TDR shift-register Register selected TDO enable Inactive TDO DS261F1 DS261PP5 DS261PP5 IDCODE Instruction register Act Inactive = Don’t care or undefined Figure 25. JTAG Instruction Register update CS61584A CS61584A New Instruction Old data Active Inactive 37 37 ...
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... Parallel Input to TDR TDR shift-register Parallel output of TDR Register Selected Inactive TDO enable TDO 38 38 DS261PP5 Instruction Old data Test data register Active Inactive = Don’t care or undefined Figure 26. JTAG Data Register update CS61584A CS61584A IDCODE New data Active Inactive DS261PP5 DS261F1 ...
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... TV SAD4 P/S RTIP1 RV+1 AGND AV+ CS61584A CS61584A Host Mode Hardware Mode Serial Port DV+ DV+ DV+ DGND3 DGND3 DGND3 CON02 not used AD4 CON11 not used AD5 AD6 CON12 not used CON21 not used AD7 CON22 not used ALE(AS) CON31 not used ...
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... TV SAD4 P/S RV+1 AV+ CS61584A CS61584A Host Mode Hardware Mode Serial Port DV+ DV+ DGND3 DGND3 CON02 not used CON11 not used CON12 not used CON21 not used CON22 not used CON31 not used not used not used RCLK2 RCLK2 62 61 RPOS2 ...
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... One-times Clock Frequency Select (PLCC pin 38; TQFP pin 28) When 1XCLK is high, REFCLK must clock (i.e., 1.544 MHz for T1 applications or 2.048 MHz for E1 applications). When 1XCLK is low, REFCLK must clock (i.e., 12.352 MHz for T1 applications or 16.384 MHz for E1 applications). DS261PP5 DS261F1 DS261PP5 CS61584A CS61584A 41 41 ...
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... Hardware mode operation is selected when MODE is low, enabling the device to be configured and monitored using control pins. Host mode operation is selected when MODE is high, enabling the device to be configured and monitored over a microprocessor interface using the internal register set DS261PP5 CS61584A CS61584A DS261PP5 DS261F1 ...
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... BTS is low. Motorola bus timing is selected when BTS is high and the pin function is listed in parenthesis "( )" Chip Select [Host mode] (PLCC pin 8; TQFP pin 64) This pin must be low in order to access the serial or parallel port of the device. DS261F1 DS261PP5 DS261PP5 CS61584A CS61584A 43 43 ...
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... DTACK - Data Acknowledge [Host mode - parallel port, BTS = 1] (PLCC pin 44; TQFP pin 33) When the BTS pin is high (Motorola bus timing), a low pulse on DTACK indicates when the CS61584A has latched the data during a microprocessor write cycle or when the CS61584A has output data to the bus during a microprocessor read cycle ...
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... J-TDO - JTAG Test Data Out (PLCC pin 17; TQFP pin 8) JTAG data is shifted out of the device on this pin. This pin is active only when JTAG testing is in progress. J-TDO will be updated on the falling edge of J-TCK. DS261PP5 DS261F1 DS261PP5 CS61584A CS61584A 9 zeros in 8192 bits ...
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... BSC 0.484 0.393 BSC 0.398 0.472 BSC 0.484 0.393 BSC 0.398 0.020 BSC 0.024 0.024 0.030 4° 7.000° CS61584A CS61584A A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.20 0.27 11.70 12.0 BSC 12 ...
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... JEDEC #: MS-047 CS61584A CS61584A e D2/ MILLIMETERS MIN NOM MAX 4.191 4.6355 5.08 2.286 2.667 3.302 0.4318 0.533 25.146 25.273 24.13 24.206 24 ...
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... Table 13. CS61584A External Components mary prevents output stage imbalances from pro- ducing a DC current through the transformer that might saturate the transformer and result in an out- put level offset. In the receive line interface circuitry, resistors R1- R4 provide receive impedance matching and re- ceiver return loss. The 0.47 µ ...
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... Figure 28. Host Mode Serial Port Configuration Vcc DTACK CS INT RD(DS) P/S WR(R/W) Host Control Channel 1 Channel 2 Power Supply TV+2 TV+1 TGND1 RGND2 RV+2 0.1 F 0 CS61584A CS61584A INT SCLK SDO SDI T1 TTIP1 C1 0.47 F TRING1 R1 T2 RTIP1 0.47 F RRING1 R2 T3 TTIP2 C2 0.47 F TRING2 R3 T4 RTIP2 0 ...
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... Power Supply As shown in Figure 27, the CS61584A operates from a 3.3 Volt or 5.0 Volt supply. Separate power and ground pins provide internal isolation. The best way to configure the power supplies is to connect all of the supply pins together at the device. The various ground pins must not be more negative than AGND. A 4.99 k ± ...
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... Transformers Recommended transformer specifications are shown in Table 17. Based on these specifications, the transformers recommended for use with the CS61584A are listed in Table 18. Turns ratio (-IL3 and IQ3) 1:2 step-up transmit 1:2 step-down receive Turns ratio (-IL5 and IQ5) 1:1.15 step-up transmit 1:1 ...
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... PE-65870 1.5 kV surface mount, dual T1016 1.5 kV surface mount, quad T1072 1.5 kV surface mount, octal 67124840 1.5 kV through-hole, single extended temperature ST5112 2.0 kV surface mount, dual ST5171T 1.5 kV surface mount, quad Table 18. Recommended Transformers CS61584A CS61584A Package Type DS261PP5 DS261F1 ...
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... ORDERING INFORMATION Model CS61584A-IL3 CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ3Z (Lead Free) CS61584A-IQ5 CS61584A-IQ5Z (Lead Free) ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS61584A-IL3 CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ3Z (Lead Free) CS61584A-IQ5 CS61584A-IQ5Z (Lead Free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS261F1 Operating Voltage Package 3 ...
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... AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 54 www.cirrus.com CS61584A Changes DS261F1 ...