Telecom Voice Conditioning ICs Phone Line Equalizer Group Delay Tuned

ML2021IP

Manufacturer Part NumberML2021IP
DescriptionTelecom Voice Conditioning ICs Phone Line Equalizer Group Delay Tuned
ManufacturerFairchild Semiconductor
ML2021IP datasheet
 


Specifications of ML2021IP

Mounting StyleThrough HolePackage / CaseDIP-16
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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ML2021
Telephone Line Equalizer
Features
• Slope, height, and bandwidth adjustable
• Optimized group delays (500 Hz to 6.4 kHz)
• On chip anti-alias filter
• Bypass mode
• Low supply current 6 mA typical from ±5V supplies
• TTL / CMOS compatible interface
• Double buffered data latch
• Selectable master clock 1.544 or 1.536 MHz
• Synchronous or asynchronous data loading capability
• Compatible with ML2003 and ML2004 logarithmic
gain/attenuator
Block Diagram
CLKSEL
V
AGND
CC
CLOCK
SMOOTHING
CLK
GENERATOR
FILTER
ANTIALIAS
V
IN
MUX
LO PASS
SLOPE
HEIGHT
BANDPASS
SECTION
SECTION
SECTION
P
DN
5
4
LATI
14-BIT LATCH
14
SID
14-BIT SHIFT REGISTER
SCK
LATO
General Description
The ML2021 is a monolithic analog line equalizer for tele-
phone applications. The ML2021 consists of a switched
capacitor filter that realizes a family of frequency response
curves optimized for telephone line equalization while mini-
mizing group delay.
The ML2021 consists of a continuous anti-aliasing filter,
three programmable switched capacitor equalization filters,
an output smoothing filter, a 600 Ω driver, and a digital
section for the serial interface.
The equalization filters adjust the slope, height, and band-
width of the frequency response. The desired frequency
response is programmed by a digital 14-bit serial input data
stream.
V
SS
CLKSEL
V
OUT
1
4
GND
CLKSEL
SOD
www.fairchildsemi.com
Pin Connections
ML2021
16-PIN DIP
1
16
V
CC
SID
2
15
P
DN
NC
3
14
V
OUT
LATO
4
13
AGND
SCK
5
12
V
IN
NC
6
11
V
SS
SOD
7
10
LATI
CLK
8
9
GND
TOP VIEW
ML2021
18-PIN SOIC
V
1
18
CC
P
SID
2
17
DN
3
16
V
NC
OUT
4
15
LATO
AGND
5
14
SCK
NC
6
13
NC
V
IN
7
12
SOD
NC
8
11
V
CLK
SS
9
10
LATI
GND
TOP VIEW
REV. 1.1.1 3/19/01

ML2021IP Summary of contents

  • Page 1

    ML2021 Telephone Line Equalizer Features • Slope, height, and bandwidth adjustable • Optimized group delays (500 Hz to 6.4 kHz) • On chip anti-alias filter • Bypass mode • Low supply current 6 mA typical from ±5V supplies • TTL ...

  • Page 2

    ML2021 Pin Description Name CLKSEL Clock select input. This pin selects the frequency of the CLK input. If CLK is 1.536 MHz, set CLKSEL = 1. If CLK is 1.544 MHz, set CLKSEL = 0. Pin has an internal pullup ...

  • Page 3

    PRODUCT SPECIFICATION Electrical Characteristics Unless otherwise specifi MIN = 600 Ω , dBm measurements use 600 Ω as reference load, V Other Bits = 100pF 1kHz sinusoid CLK = 1.544 ...

  • Page 4

    ML2021 Electrical Characteristics Unless otherwise specifi MIN Other Bits = 100pF 600Ω, dBm measurements use 600Ω as reference load 1kHz sinusoid CLK = 1.544 MHz ±300 Hz and ...

  • Page 5

    PRODUCT SPECIFICATION SCK SID SOD SCK LATI LATO SOD TIMING PARAMETERS ARE REFERENCED TO THE 1.4 VOLT MIDPOINT. 12 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0 –1.5 –3.0 0 500 1000 1500 2000 2500 FREQUENCY (Hz) Figure 2. Typical ...

  • Page 6

    ML2021 12 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0 –1.5 –3.0 0 500 1000 1500 2000 2500 3000 FREQUENCY (Hz) Figure 3. Typical Slope Filter Response—NL 10.5 1111 9.0 7.5 1000 6.0 4.5 0100 3.0 0010 ...

  • Page 7

    PRODUCT SPECIFICATION Functional Description The ML2021 consists of a continuous anti-alias filter, three programmable switched capacitor equalization filters, an output smoothing filter, an output driver, and a digital section for the serial interface. Anti-Alias Filter The first section is a ...

  • Page 8

    ML2021 Table 3. Slope Response Factors (b, S3 0000 2.371759E +03 1.116280E + 04 0001 1.985920E + 03 9.345141E + 03 0010 1.701779E + 03 8.007156E + 03 0011 1.493571E + 03 ...

  • Page 9

    PRODUCT SPECIFICATION high. The LATI pulse must occur when SCK is low. A new data word can be loaded into the shift register without dis- turbing the existing data word in the latch. The parallel outputs of the latch control ...

  • Page 10

    ML2021 Powerdown Mode A powerdown mode can be selected with pin the device is powered down. In this state, the power DN consumption is reduced by removing power from the analog section and forcing the analog ...

  • Page 11

    ... ML2021 Ordering Information Part Number ML2021CP ML2021CS ML2021IP ML2021IS DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; ...