LAN9115-MD SMSC, LAN9115-MD Datasheet
LAN9115-MD
Specifications of LAN9115-MD
Related parts for LAN9115-MD
LAN9115-MD Summary of contents
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... Reduces system cost and increases design flexibility — SRAM-like interface easily interfaces to most Embedded CPU’s or SoC’s — Low-cost, low--pin count non-PCI interface for embedded designs SMSC LAN9115 LAN9115 Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller Reduced Power Modes — ...
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... LAN9115-MT FOR 100 PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... Hardware Reset Input (nRESET 3.11.3 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.11.4 Soft Reset (SRST 3.11.5 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.12 MII Interface - External MII Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.12.1 SMI Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.12.2 MII Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.13 TX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.13.1 TX Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SMSC LAN9115 3 DATASHEET Revision 1.5 (07-11-08) ...
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... ID_REV—Chip ID and Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.2 IRQ_CFG—Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.3 INT_STS—Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.4 INT_EN—Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.5 BYTE_TEST—Byte Order Test Register 5.3.6 FIFO_INT—FIFO Level Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 4 DATASHEET Datasheet SMSC LAN9115 ...
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... Special Restrictions on Back-to-Back Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2 PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3 PIO Burst Reads 122 6.4 RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.5 RX Data FIFO Direct PIO Burst Reads 124 6.6 PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SMSC LAN9115 5 DATASHEET Revision 1.5 (07-11-08) ...
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... Power Consumption Device Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.4 Power Consumption Device and System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 6 DATASHEET Datasheet SMSC LAN9115 ...
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... Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet List of Figures Figure 1.1 System Block Diagram Utilizing the SMSC LAN9115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 1.2 Internal Block Diagram Figure 2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3.1 VLAN Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 3.2 VLAN Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 3.3 EEPROM Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 3 ...
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... Table 5.5 Backpressure Duration Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 5.6 LAN9115 MAC CSR Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 5.8 LAN9115 PHY Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 5.9 MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 6.1 Read After Write Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 6 ...
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... The LAN9115 also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9115 can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions ...
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... Figure 1.1 System Block Diagram Utilizing the SMSC LAN9115 The SMSC LAN9115 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets. The LAN9115 Ethernet MAC/PHY controller is designed and optimized to function in an embedded environment. All communication is performed with programmed I/O transactions using the simple SRAM-like host interface bus ...
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... GP Timer 1.2 10/100 Ethernet PHY The LAN9115 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be configured for either 100 Mbps (100Base-TX Mbps (10Base-T) Ethernet operation in either full or half duplex configurations. The PHY block includes auto-negotiation. Minimal external components are required for the utilization of the Integrated PHY. ...
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... The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with programmable polarity. 1.7 Serial EEPROM Interface A serial EEPROM interface is included in the LAN9115. The serial EEPROM is optional and can be programmed with the LAN9115 MAC address. The LAN9115 can optionally load the MAC address automatically after power-on. 1.8 ...
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... External MII Interface The LAN9115 also supports the ability to interface to an external PHY device. This interface is compatible with all IEEE 802.3 MII compliant physical layer devices. For additional information on the MII interface and associated signals, please refer to Switching," ...
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... Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller SMSC LAN9115 100 PIN TQFP Figure 2.1 Pin Configuration 14 DATASHEET Datasheet 50 D10 49 D11 48 VDD_IO 47 GND_IO 46 D12 45 D13 44 D14 43 D15 42 VDD_IO 41 GND_IO 40 TX_CLK 39 TXD0 38 TXD1 37 TXD2 36 TXD3 35 VDD_IO 34 GND_IO 33 COL 32 CRS 31 MDC 30 MDIO** 29 RX_DV 28 VDD_IO 27 GND_IO 26 RX_CLK SMSC LAN9115 ...
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... LAN9115 when reduced power state. Programmable Interrupt request. Programmable polarity, source and buffer types. When driven high all accesses to the LAN9115 are to the Data FIFOs. In this mode, the A[7:3] upper address inputs are ignored. AUTO NEG. DISABLED ENABLED Revision 1.5 (07-11-08) ...
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... When configured as a GPO signal RX_DV/RX_CLK monitor, the EECS pin is deasserted never unintentionally access the serial EEPROM. This signal cannot function as a general- purpose input. Note: When the EEPROM interface is not used, the EECLK pin must be left unconnected. SMSC LAN9115 ...
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... See Section 3.11, "Detailed Reset Description," on page 42 for additional information When programmed to do so, is asserted when the LAN9115 detects a wake event and is requesting the system to wake up from the associated sleep state. The polarity and buffer type of this signal is programmable. Note: ...
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... This signal is driven high only during 10Mbs operation. nLED2 (Link & Activity Indicator). This signal is driven low (LED on) when the LAN9115 detects a valid link. This signal is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This signal is then driven low again for a ...
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... Note 2.1 Please refer to the SMSC application note AN 12.5 titled “Designing with the LAN9118 - Getting Started” also important to note that this application note applies to the whole SMSC LAN9118 family of Ethernet controllers. However, subtle differences may apply. SMSC LAN9115 BUFFER NUM TYPE ...
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... IO bus pin. External PHY Detect: This pin also functions as a strap input, which can be used to indicate the presence of an external PHY. See Note 2.2. Note: See Section 5.3.9, "HW_CFG—Hardware Configuration Register" for more information on SMI_SEL and EXT_PHY_DET SMSC LAN9115 ...
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... Datasheet Table 2.6 MII Interface Signals (continued) PIN NO. NAME 31 Management Data Clock Note 2.2 The external SMI port is selected when SMI_SEL = 1. When SMI_SEL = 0, MDIO is tri- stated and MDC is driven low. SMSC LAN9115 BUFFER NUM SYMBOL TYPE PINS MDC O8 (PD DATASHEET DESCRIPTION ...
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... PU 50uA (typical) internal pull-down PD Analog input AI Analog output AO Analog bi-directional AIO Crystal oscillator input pin ICLK Crystal oscillator output pin OCLK Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Table 2.7 Buffer Types DESCRIPTION 22 DATASHEET Datasheet SMSC LAN9115 ...
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... Generation of control frames Interface to the internal PHY and optional external PHYl The transmit and receive data paths are separate within the LAN9115 from the MAC to host interface allowing the highest performance, especially in full duplex mode. Payload data as well as transmit and receive status are passed on these busses. ...
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... Flow Control The LAN9115 Ethernet MAC supports full-duplex flow control using the pause operation and control frame. It also supports half-duplex flow control using back pressure. 3.2.1 Full-Duplex Flow Control The pause operation inhibits data transmission of data frames for a specified period of time. A Pause ...
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... The tag structure was proprietary until the IEEE released a supplement to 802.3 defining the VLAN frame structure, including the tag. This new frame structure for VLAN is depicted in Figure 3.2, "VLAN Frame". SMSC LAN9115 VLAN 2 CCC ...
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... VLAN tag adds to the frame. The maximum length of the good packet is thus changed from 1518 bytes to 1522 bytes. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Figure 3.2 VLAN Frame 26 DATASHEET Datasheet SMSC LAN9115 ...
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... The first bit of the destination address signifies whether physical address or a multicast address. The LAN9115 address check logic filters the frame based on the Ethernet receive filter mode that has been enabled. Filter modes are specified based on the state of the control bits in Filtering Modes" ...
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... Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9115 Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into the MAC Address High register and the MAC Address Low register. If the incoming frame is a multicast frame, however, the LAN9115 packet filter function performs an imperfect address filtering against the hash table ...
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... Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled. The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined by Filter i. SMSC LAN9115 Register, a broadcast wake-up frame will wake-up the device despite Filter 0 Byte Mask ...
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... MAC examines receive data for a Magic Packet. The LAN9115 can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or assertion of the power managment event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the WUCSR is set ...
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... It should be noted that Magic Packet detection can be performed when LAN9115 is in the power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when the device enters the D1 state. ...
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... LAN Driver to set the IEEE addresses. The LAN9115 EEPROM controller also allows the host system to read, write and erase the contents of the Serial EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation ...
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... Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM the host must first issue the EWEN command operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9115 will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set. ...
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... Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller EEPROM Read Idle Write Data Register Write Command Register Read Command Register Section 5.3.23, "E2P_CMD – EEPROM Command Register," DATASHEET Datasheet Idle Write Command Register Read Command Register Busy Bit = 0 Read Data Register SMSC LAN9115 ...
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... ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) SMSC LAN9115 Figure 3.4 EEPROM ERASE Cycle Figure 3 ...
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... Note: The EEPROM device will power-up in the erase/write-disabled state. Any erase or write operations will fail until an Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Figure 3.6 EEPROM EWDS Cycle Figure 3.7 EEPROM EWEN Cycle 36 DATASHEET Datasheet t CSL t CSL SMSC LAN9115 ...
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... E2P_DATA register to be written to the EEPROM location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) SMSC LAN9115 Figure 3.8 EEPROM READ Cycle Figure 3 ...
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... Figure 3.10 EEPROM WRAL Cycle Cycles", shown below, shows the number of EECLK cycles required for Table 3.8 Required EECLK Cycles REQUIRED EECLK CYCLES for a detailed description of these registers. for detailed EEPROM timing specifications. 38 DATASHEET Datasheet t CSL and Section 5.3.24, SMSC LAN9115 ...
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... A write to the BYTE_TEST register, regardless of whether a wake-up frame or Magic Packet was detected, will return LAN9115 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device ...
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... Note 3.8 The host must do only read accesses prior to the ready bit being set. Once the READY bit is set, the LAN9115 is ready to resume normal operation. At this time the WUPS field can be cleared. 3.10.2.2 D2 Sleep In this state, as shown in placed in a reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY (Mode Control/Status register) must be set ...
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... WUPS bits clearing the corresponding WOL_EN or ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a ‘1’ to this bit in the INT_STS register. It should be noted that the LAN9115 can generate a host interrupt regardless of the state of the PME_EN bit, or the external PME signal. ...
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... Note 3.11 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data. Note 3.12 After a POR, nRESET or SRST, the LAN9115 will automatically check for the presence of an external EEPROM. After any of these resets the application must verify that the EPC ...
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... Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high. After the “READY” bit is set, the LAN9115 can be configured via its control registers. The nRESET signal is pulled-high internally by the LAN9115 and can be left unconnected if unused. If used, nRESET must be driven low for a minimum period as defined in APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -” ...
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... The LAN9115 Receiver must be halted. The halting of the LAN9115 receiver must be complete. The PHY_CLK_SEL field must be set to 10b. This action will disable the MII clocks to the LAN9115 internal logic for both the internal PHY, and the external MII interface. The host must wait a period of time not less than 5 cycles of the slowest operating clock before executing the next step in this procedure ...
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... Enable theLAN9115 transmitter. Enable the LAN9115 receiver. The process is complete. The LAN9115 is now operational using the newly selected MII device. The above procedure must be repeated each time the MII port is switched. The procedure is identical when switching from internal PHY to external MII, or vice-versa. ...
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... PHY_CLK_SEL 6 to 10b 7 Clocks Halted? YES Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 8 EXT_PHY_SEL to Desired MII Port 9 PHY_CLK_SEL to Desired MII Port Figure 3.12 MII Switching Procedure 46 DATASHEET Datasheet Set Set Clocks NO Running YES Enable RX Enable TX Complete SMSC LAN9115 ...
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... Burst length regardless of the actual packet length. When configured to do so, the LAN9115 will accept extra data at the end of the packet and will remove the extra padding before transmitting the packet. The LAN9115 automatically removes data up to the boundary specified in the Buffer End Alignment field specified in each TX command ...
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... Figure 3.13 Simplified Host TX Flow Diagram Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller init Idle TX Status Available Read TX Status (optional) Check available FIFO space Write TX Command Write Start Padding (optional) Not Last Buffer Write Buffer 48 DATASHEET Datasheet SMSC LAN9115 ...
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... The following diagram illustrates the buffer format. Host Write Figure 3.14, "TX Buffer Format", shows the TX Buffer written into the LAN9115. It should be noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must be taken into account when calculating the actual TX data FIFO usage. Please refer to " ...
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... DWORD’s were added to the end of the Buffer. A running count is also maintained in the LAN9115 of the cumulative buffer sizes for a given packet. This cumulative value is compared against the Packet Length field in the TX command ‘B’ word and if they do not correlate, the TXE flag is set ...
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... The first buffer of any transmit packet can be any length Middle buffers (i.e., those with First Segment = Last Segment = 0) must be greater than, or equal to 4 bytes in length The final buffer of any transmit packet can be any length SMSC LAN9115 Table 3.12 TX Command 'B' Format DESCRIPTION Table 3.13, "TX DATA Start Table 3 ...
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... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a Driver-supplied buffer) before the transmit packet can be sent to the LAN9115. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
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... Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” Figure 3.15, "TX Example 1" illustrates the TX command structure for this example, and also shows how data is passed to the TX data FIFO. SMSC LAN9115 DESCRIPTION 53 DATASHEET Revision 1.5 (07-11-08) ...
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... Note 3.16 The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. atomic 16-bit transactions. Data W ritten to the Ethernet Controller 31 TX Com m and 'A' Buff er End Alignment = 1 Data Start Of fset = 7 First Segment = 1 Last Segment = 0 7-Byte Data Start Offset ...
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... Ethernet Controller 31 TX Command 'A' Buffer End Alignment = 0 Data Start Offset = 6 First Segment = 1 Last Segment = 1 Buffer Size =183 TX Command 'B' Packet Length = 183 SMSC LAN9115 0 TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 3B End Padding Figure 3.16 TX Example 2 55 DATASHEET ...
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... The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9115 can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9115 is operating in a system that always performs multi-DWORD bursts ...
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... The host should perform the proper number of reads, as indicated by the packet length plus the start offset and the amount of optional padding added to the end of the frame, from the RX data FIFO. Last Packet Figure 3.17 Host Receive Routine Using Interrupts Last Packet Figure 3.18 Host Receive Routine with Polling SMSC LAN9115 init Idle RX Interrupt Read RX Status ...
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... FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be returned to their reset state. To perform a receiver dump, the LAN9115 receiver must be halted. Once the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register. The RX_DUMP bit is cleared when the dump is complete ...
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... Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Host Read Order 1st 2nd Last Note 3.17 The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. transactions. 3.14.3 RX Status Format BITS 31 Reserved. This bit is reserved. Reads 0. ...
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... Error (RXE) will be asserted under the following conditions: A host underrun of RX data FIFO A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller DESCRIPTION 60 DATASHEET Datasheet SMSC LAN9115 ...
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... F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc. The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is th bypassed the 5 transmit data bit is equivalent to TX_ER. SMSC LAN9115 100M PLL 4B/5B 25MHz MII ...
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... Sent for falling TX_EN Sent for falling TX_EN Sent for rising TX_ER INVALID INVALID INVALID INVALID INVALID INVALID INVALID 62 DATASHEET Datasheet TRANSMITTER INTERPRETATION 0 0000 DATA 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 SMSC LAN9115 ...
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... Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. SMSC LAN9115 Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 63 ...
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... Decoder 125 Mbps Serial DSP: Timing MLT-3 recovery, Equalizer and BLW Correction RJ45 MLT-3 MLT-3 6 bit Data Figure 4.2 Receive Data Path Figure 4.2. Detailed descriptions are given below. 64 DATASHEET Datasheet Descrambler 25MHz by 5 bits and SIPO CAT-5 SMSC LAN9115 ...
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... The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted SMSC LAN9115 65 DATASHEET ...
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... Auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 66 DATASHEET Datasheet SMSC LAN9115 ...
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... Auto-negotiation will also re-start if not all of the required FLP bursts are received. Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new SMSC LAN9115 67 DATASHEET ...
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... Parallel Detection If the LAN9115 is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This ability is known as “ ...
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... Mbps Note 4.1 The LAN9115 10/100 PHY CRS signal operates in two modes: Active and Low. When in Active mode, CRS will transition high and low upon line activity, where a high value indicates a carrier has been detected. In Low mode, CRS stays low and does not indicate carrier detection ...
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... Chapter 5 Register Description The following section describes all LAN9115 registers and data ports. Note 5.1 The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. transactions. FCh B4h B0h ACh A8h A4h A0h 50h 4Ch ...
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... LAN9115 registers accordingly. 5.2 RX and TX FIFO Ports The LAN9115 contains four host-accessible FIFOs: the RX Status, RX data, TX Status, and TX data FIFOs. The sizes of the RX and TX data FIFOs, as well as the RX Status FIFO are configurable through the CSRs. ...
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... The host write to any of the locations since they all access the same TX data FIFO location and perform the same function. 5.3 System Control and Status Registers Table 5.1, "LAN9115 Direct Address Register the host bus. Table 5.1 LAN9115 Direct Address Register Map BASE ADDRESS + OFFSET SYMBOL 50h ID_REV ...
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... Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 5.1 LAN9115 Direct Address Register Map (continued) BASE ADDRESS + OFFSET SYMBOL ACh AFC_CFG B0h E2P_CMD B4h E2P_DATA B8h - FCh RESERVED 5.3.1 ID_REV—Chip ID and Revision Offset: This register contains the ID and Revision fields for this design. ...
Page 74
... When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 54h Size: 74 DATASHEET Datasheet 32 bits TYPE DEFAULT R R R/W 0 NASR RO - R/W 0 NASR SMSC LAN9115 ...
Page 75
... PME hardware signal. Notes: Detection of a Power Management Event, and assertion of the PME signal will not wakeup the LAN9115. The LAN9115 will only wake up when it detects a host write cycle of any data to the BYTE_TEST register. ...
Page 76
... GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller DESCRIPTION 76 DATASHEET Datasheet TYPE DEFAULT RO - R/WC 0 R/WC 0 R/WC 0 R/ R/WC 0 R/WC 0 R/WC 000 SMSC LAN9115 ...
Page 77
... TX Status FIFO Full Interrupt (TSFF_INT_EN Status FIFO Level Interrupt (TSFL_INT_EN Dropped Frame Interrupt Enable (RXDF_INT_EN) 5 Reserved 4 RX Status FIFO Full Interrupt (RSFF_INT_EN Status FIFO Level Interrupt (RSFL_INT_EN) 2-0 GPIO [2:0] (GPIOx_INT_EN). SMSC LAN9115 5Ch Size: 77 DATASHEET 32 bits TYPE DEFAULT R R/W 0 ...
Page 78
... When the RX Status FIFO used space is greater than this value an RX Status FIFO Level interrupt (RSFL) will be generated. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 64h Size: 68h Size: 78 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 87654321h 32 bits TYPE DEFAULT R/W 48h R/W 00h RO - R/W 00h SMSC LAN9115 ...
Page 79
... BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9115 will add extra DWORDs of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORDs. This mechanism can be used to maintain cache line alignment on host processors ...
Page 80
... TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN9115 Ethernet Controller. BITS DESCRIPTION 31-16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero ...
Page 81
... HW_CFG—Hardware Configuration Register Offset: This register controls the hardware configuration of the LAN9115 Ethernet Controller. Note: The transmitter and receiver must be stopped before writing to this register. Refer to 3.13.8, "Stopping and Starting the Transmitter," on page 56 Starting the Receiver," on page 60 ...
Page 82
... The internal RX_CLK and TX_CLK signals must be running for a proper software reset. Please refer to Section 6.8, "Reset Timing," on page 127 The LAN9115 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. 5.3.9.1 Allowable settings for Configurable FIFO Memory Allocation TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above ...
Page 83
... Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX data FIFO. Conversely, as data is received by the LAN9115 moved from the MAC to the RX MIL FIFO, and then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO ...
Page 84
... RX_FFWD. 30-0 Reserved 5.3.11 RX_FIFO_INF—Receive FIFO Information Register Offset: This register contains the used space in the receive FIFOs of the LAN9115 Ethernet Controller. BITS DESCRIPTION 31-24 Reserved 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO ...
Page 85
... Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.12 TX_FIFO_INF—Transmit FIFO Information Register Offset: This register contains the free space in the transmit data FIFO and the used space in the transmit status FIFO in the LAN9115. BITS DESCRIPTION 31-24 Reserved 23-16 TX Status FIFO Used Space (TXSUSED). Indicates the amount of space in DWORDS used in the TX Status FIFO ...
Page 86
... Offset: This register controls the Power Management features. This register can be read while the power saving mode. LAN9115 Note: The LAN9115 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. BITS DESCRIPTION ...
Page 87
... Device Ready (READY). When set, this bit indicates that LAN9115 is ready to be accessed. This register can be read when LAN9115 is in any power management mode. Upon waking from any power management mode, including power-up, the host processor can interrogate this field as an indication when LAN9115 has stabilized and is fully alive ...
Page 88
... GPIO2 – bit 10 7:5 Reserved Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 88h Size: Description for the EEPROM Enable bit function definitions. 88 DATASHEET Datasheet 32 bits Type Default RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 0000 RO - SMSC LAN9115 ...
Page 89
... Timer is put into the run state. When cleared, the GP Timer is halted. On the transition of this bit the GPT_LOAD field will be preset to FFFFh. 28-16 Reserved 15-0 General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded into the GP-Timer. SMSC LAN9115 Description EEDIO FUNCTION EEDIO GPO3 Reserved GPO3 ...
Page 90
... This register controls how words from the host data bus are mapped to the CRSs and Data FIFOs inside the LAN9115. The LAN9115 always sends data from the Transmit Data FIFO to the network so that the low order word is sent first, and always receives data from the network to the Receive Data FIFO so that the low order word is received first ...
Page 91
... DESCRIPTION 31-0 RX Dropped Frame Counter (RX_DFC). This counter is incremented every time a receive frame is dropped. RX_DFC is cleared on any read of this register. An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). SMSC LAN9115 9Ch Size: A0h Size: 91 DATASHEET 32 bits ...
Page 92
... MAC CSR Data. Value read from or written to the MAC CSR’s. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller A4h Size: A8h Size: 92 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 00h 32 bits TYPE DEFAULT R/W 00000000h SMSC LAN9115 ...
Page 93
... AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9115 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS DESCRIPTION ...
Page 94
... BITS DESCRIPTION 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9115 will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9115 is operating in full-duplex mode. ...
Page 95
... Note: EPC busy will be high immediately following power-up or reset. After the EEPROM controller has finished reading (or attempting to read) the MAC address from the EEPROM the EPC Busy bit is cleared. SMSC LAN9115 B0h Size: 95 DATASHEET 32 bits TYPE ...
Page 96
... MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. 27-10 Reserved. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller [28] OPERATION 0 READ 1 EWDS 0 EWEN 1 WRITE 0 WRAL 1 ERASE 0 ERAL 1 Reload 96 DATASHEET Datasheet TYPE DEFAULT R SMSC LAN9115 ...
Page 97
... This register is used in conjunction with the E2P_CMD register to perform read and write operations with the Serial EEPROM BITS DESCRIPTION 31-8 Reserved. 7:0 EEPROM Data. Value read from or written to the EEPROM. SMSC LAN9115 When set, this bit indicates that a valid EEPROM B4h Size: 97 DATASHEET TYPE DEFAULT ...
Page 98
... MAC_CSR_CMD and MAC_CSR_DATA registers (see sections MAC_CSR_CMD – MAC CSR Synchronizer Command Register and MAC_CSR_DATA – MAC CSR Synchronizer Data Register). Table 5.6 LAN9115 MAC CSR Register Map MAC CONTROL AND STATUS REGISTERS INDEX ...
Page 99
... Pass Bad Frames (PASSBAD). When set, all incoming frames that passed address filtering are received, including runt frames and collided frames. 15 Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses 14 Reserved SMSC LAN9115 1 Attribute: 00040000h Size: DESCRIPTION 99 ...
Page 100
... BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9115 will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register. ...
Page 101
... Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of the LAN9115 device. The content of this field is undefined until loaded from the EEPROM at power- on. The host can update the contents of this field after the initialization process has completed. ...
Page 102
... Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the LAN9115 device. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. ...
Page 103
... HASHL—Multicast Hash Table Low Register Offset: Default Value: This register defines the lower 32-bits of the Multicast Hash Table. Please refer to "HASHH—Multicast Hash Table High Register" BITS 31-0 Lower 32 bits of the 64-bit Hash Table SMSC LAN9115 4 Attribute: 00000000h Size: DESCRIPTION 5 Attribute: ...
Page 104
... MII Busy (MIIBZY): This bit must be polled to determine when the MII register accesss is complete. This bit must read a logical 0 before writing to this register and MII data register. The LAN driver software must set (1) this bit in order for the LAN9115 to read or write any of the MII PHY registers. ...
Page 105
... Enable (FCEN) bit enables the receive portion of the Flow Control block. This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The LAN9115 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31-16 Pause Time (FCPT) ...
Page 106
... VLAN2 frame detection.If used, this register must be set to 0x8100. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 9 Attribute: 00000000h Size: DESCRIPTION A Attribute: 00000000h Size: DESCRIPTION 106 DATASHEET Datasheet R/W 32 bits R/W 32 bits SMSC LAN9115 ...
Page 107
... Wake-Up Frame enabled (WUEN). When set, Remote Wake-Up mode is enabled and the MAC is capable of detecting wake-up frames as programmed in the wake-up frame filter. 1 Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. 0 Reserved SMSC LAN9115 B Attribute: 00000000h Size: DESCRIPTION C Attribute: ...
Page 108
... PHY Register Indexes are shown in Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. Table 5.8 LAN9115 PHY Control and Status Register PHY CONTROL AND STATUS REGISTERS INDEX REGISTER NAME ...
Page 109
... Collision Test enable COL test disable COL test 6-0 Reserved Note 5.2 This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details SMSC LAN9115 0 Size: 109 DATASHEET 16-bits TYPE DEFAULT RW/SC ...
Page 110
... Jabber Detect jabber condition detected jabber condition detected 0 Extended Capabilities supports extended capabilities registers 0 = does not support extended capabilities registers. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 1 Size: 110 DATASHEET Datasheet 16-bits TYPE DEFAULT RO/ RO/LL 0 RO/ SMSC LAN9115 ...
Page 111
... PHY Identifier 2 Index (In Decimal): BITS DESCRIPTION 15-10 PHY ID Number b. Assigned to the 19th through 24th bits of the OUI Model Number. Six-bit manufacturer’s model number Revision Number. Four-bit manufacturer’s revision number. SMSC LAN9115 2 Size: 3 Size: 111 DATASHEET 16-bits TYPE DEFAULT RO ...
Page 112
... Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 4 Size: 5.3) 112 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 00 R/W 0 R R/W See Note 5.4 R/W 1 R/W See Note 5.4 R/W See Note 5.4 R/W 00001 SMSC LAN9115 ...
Page 113
... Full Duplex with full duplex full duplex ability 7 100Base-TX able ability 6 10Base-T Full Duplex 10Mbps with full duplex 10Mbps with full duplex ability 5 10Base- 10Mbps able 10Mbps ability 4:0 Selector Field. [00001] = IEEE 802.3 SMSC LAN9115 5 Size: 113 DATASHEET 16-bits TYPE DEFAULT ...
Page 114
... Reset to “1” by hardware reset, unaffected by SW reset. 0 Reserved. Write as “0”. Ignore on read. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 6 Size: 17 Size: 114 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0 RO/ RO/ 16-bits TYPE DEFAULT SMSC LAN9115 ...
Page 115
... Half Duplex is advertised. Auto- negotiation enabled. CRS is active during Transmit & Receive. 101 Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive. 110 Reserved - Do not set the LAN9115 in this mode. 111 All capable. Auto-negotiation enabled. SMSC LAN9115 18 Size: DESCRIPTION Table 5.9 for more details ...
Page 116
... INT1. 1= Auto-Negotiation Page Received, 0= not source of interrupt 0 Reserved. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller 27 Size: DESCRIPTION 29 Size: 116 DATASHEET Datasheet 16-bits MODE DEFAULT RW 0 RW, 0 NASR 1011b 16-bits TYPE DEFAULT RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 SMSC LAN9115 ...
Page 117
... Speed Indication. HCDSPEED value: [001]=10Mbps half-duplex [101]=10Mbps full-duplex [010]=100Base-TX half-duplex [110]=100Base-TX full-duplex 1-0 Reserved. Write as 0; ignore on Read Note 5.5 See Table 2.2, “Default Ethernet Settings,” on page SMSC LAN9115 30 Size: 31 Size: 15, for default settings. 117 DATASHEET 16-bits TYPE ...
Page 118
... In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced. These periods are specified in processor is required to wait the specified period of time after any write to the LAN9115 before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle ...
Page 119
... RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPIO_CFG GPT_CFG GPT_CNT WORD_SWAP FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG E2P_CMD E2P_DATA SMSC LAN9115 Table 6.1 Read After Write Timing Rules MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) 0 165 165 165 0 165 165 165 165 165 ...
Page 120
... There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9115, and the subsequent indication of the expected change in the control register values. ...
Page 121
... Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles. A[7:1] nCS, nRD Data Bus Figure 6.1 LAN9115 PIO Read Cycle Timing Note: The “Data Bus” width is 16 bits SYMBOL DESCRIPTION t Read Cycle Time ...
Page 122
... Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between bursts for the period specified. A[7:5] A[4:1] nCS, nRD Data Bus Figure 6.2 LAN9115 PIO Burst Read Cycle Timing Note: The “Data Bus” width is 16 bits SYMBOL DESCRIPTION t nCS, nRD Deassertion Time ...
Page 123
... RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9115 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9115 ...
Page 124
... RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9115 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9115 ...
Page 125
... Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.6 PIO Writes PIO writes are used for all LAN9115 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. A[7:1] ...
Page 126
... TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9115 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9115 ...
Page 127
... PARAMETER DESCRIPTION T6.1 Reset Pulse Width T6.2 Configuration input setup to nRST rising T6.3 Configuration input hold after nRST rising T6.4 Output Drive after nRST rising SMSC LAN9115 T6.1 T6.2 T6.3 T6.4 Table 6.9 Reset Timing MIN TYP MAX 200 200 10 16 ...
Page 128
... EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9115 SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK Low time CKL t EECS high before rising edge of EECLK CSHCKH t EECLK falling edge to EECS low CKLCSL t EEDIO valid before rising edge of EECLK ...
Page 129
... Section 7.2, "Operating applicable section of this specification is not implied. 7.2 Operating Conditions** Supply Voltage (VDD_A, VDD_REF, VREG, VDD_IO +3.3V +/- 10% Ambient Operating Temperature in Still Air (T **Proper operation of the LAN9115 is guaranteed only within the ranges specified in this section. SMSC LAN9115 (Note 7. .0V to +3.3V+10% (Note 7. +6V (Note 7 ...
Page 130
... Each LED indicator in use adds approximately the Digital power supply. Note 7 Normal Operation WOL (Wake On LAN mode), D2= Low Power Energy Detect. Revision 1.5 (07-11-08) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller TOTAL POWER - TYPICAL (MW) 130 DATASHEET Datasheet 244 225 120 120 35 11 422 367 262 262 35 11 SMSC LAN9115 ...
Page 131
... D2, General Power Down 100BASE-TX Operation D0, 100BASE-TX /w traffic D0, Idle D1, 100BASE-T /w traffic D1, Idle D2, Energy Detect Power Down D2, General Power Down Note 7.6 Each LED indicator in use adds approximately the Digital power supply. SMSC LAN9115 TOTAL POWER - TYPICAL (MW) 131 DATASHEET 614 637 513 513 56 32 ...
Page 132
... VDD - 0.4 0.4 -0.3 0.8 2.0 5.5 0.4 VDD - 0.4 0.4 0.4 VDD - 0.4 -0.3 0.5 1.4 3.6 132 DATASHEET Datasheet UNITS NOTES Schmitt Trigger V Schmitt Trigger 12mA -12mA 12mA 8mA -8mA 8mA 8mA -8mA SMSC LAN9115 ...
Page 133
... Note 7.9 Measured differentially. Table 7.5 10BASE-T Tranceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Note 7.10 Measured at the line side of the transformer, line replaced by 100Ω (+/- 1%) resistor. SMSC LAN9115 SYMBOL MIN TYP MAX V 950 - 1050 PPH ...
Page 134
... Clock Circuit The LAN9115 can accept either a 25MHz crystal (preferred MHz clock oscillator (±50 PPM) input. The LAN9115 shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1 (pin 6). If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3 ...
Page 135
... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN9115 MAX REMARKS 1.60 Overall Package Height 0 ...
Page 136
... Section 7.2, other external devices.” These specifications are not needed by the customer since the regulators are not to be used for external applications. 136 DATASHEET Datasheet CORRECTION WUCSR—Wake- Register, a broadcast wake- Register.” SMSC LAN9115 ...