HEF40193BPN NXP Semiconductors, HEF40193BPN Datasheet - Page 2

• Manufacturer Part Number: HEF40193BPN
• Description: Counter ICs 4-BIT U/D BIN COUNTR
• Manufacturer: NXP Semiconductors

Specifications of HEF40193BPN

• Counter Type: Binary Counters
• Mounting Style: SMD/SMT
• Package / Case: SOT-38
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HEF40193BP,652

Philips Semiconductors
DESCRIPTION
The HEF40193B is a 4-bit synchronous up/down
binary counter. The counter has a count-up clock input
(CP
parallel load input (PL), four parallel data inputs (P
an asynchronous master reset input (MR), four counter
outputs (O
(carry) output (TC
count-down (borrow) output (TC
PINNING
January 1995
PL
P
CP
CP
MR
TC
TC
O
0
4-bit up/down binary counter
0
U
to P
U
D
U
D
to O
), a count-down clock input (CP
3
3
0
to O
parallel load input (active LOW)
parallel data inputs
count-up clock pulse input (LOW to HIGH,
edge-triggered)
count-down clock pulse input (LOW to
HIGH, edge-triggered)
master reset input (asynchronous)
buffered terminal count-up (carry) output
(active LOW)
buffered terminal count-down
(borrow) output (active LOW)
buffered counter outputs
Fig.1 Functional diagram.
3
), an active LOW terminal count-up
U
) and an active LOW terminal
D
).
D
), an asynchronous
0
to P
3
),
2
The counter outputs change state on the LOW to HIGH
transition of either clock input. However, for correct
counting, both clock inputs cannot be LOW
simultaneously. The outputs TC
HIGH. When the circuit has reached the maximum count
state of ‘15’, the next HIGH to LOW transition of CP
cause TC
HIGH again. Likewise, output TC
circuit is in the zero state and CP
LOW, the information on P
loaded into the counter. A HIGH on MR resets the counter
independent of all other input conditions. The counter
stages are of a static toggle type flip-flop.
FAMILY DATA, I
See Family Specification
HEF40193BP(N): 16-lead DIL; plastic
HEF40193BD(F): 16-lead DIL; ceramic (cerdip)
HEF40193BT(D): 16-lead SO; plastic
( ): Package Designator North America
U
to go LOW. TC
DD
Fig.2 Pinning diagram.
LIMITS category MSI
(SOT38-1)
(SOT74)
(SOT109-1)
U
0
to P
will stay LOW until CP
U
D
3
D
and TC
is asynchronously
goes LOW. When PL is
Product specification
will go LOW when the
HEF40193B
D
are normally
MSI
U
U
goes
will