MTB2P50ET4G ON Semiconductor, MTB2P50ET4G Datasheet - Page 5

• Manufacturer Part Number: MTB2P50ET4G
• Description: MOSFET P-CH 500V 2A D2PAK
• Manufacturer: ON Semiconductor

Specifications of MTB2P50ET4G

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 6 Ohm @ 1A, 10V
• Drain To Source Voltage (vdss): 500V
• Current - Continuous Drain (id) @ 25° C: 2A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 27nC @ 10V
• Input Capacitance (ciss) @ Vds: 1183pF @ 25V
• Power - Max: 2.5W
• Mounting Type: Surface Mount
• Package / Case: D²Pak, TO-263 (2 leads + tab)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
Resistance−General Data and Its Use.”
traverse any load line provided neither rated peak current
(I
transition time (t
power averaged over a complete switching cycle must not
exceed (T
in switching circuits with unclamped inductive loads. For
DM
The Forward Biased Safe Operating Area curves define
Switching between the off−state and the on−state may
A Power MOSFET designated E−FET can be safely used
12
10
8
6
4
2
0
Figure 8. Gate−To−Source and Drain−To−Source
) nor rated voltage (V
0
Q
2
J(MAX)
1
in
4
Voltage versus Total Charge
r
,t
Q
− T
f
3
) do not exceed 10 ms. In addition the total
C
6
Q
AN569,
)/(R
T
, TOTAL CHARGE (nC)
Q
8
2
qJC
).
10
Q
DSS
T
1.6
1.2
0.8
0.4
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
) is exceeded and the
2
0
“Transient
0.6
12
Figure 10. Diode Forward Voltage versus Current
V
T
14
0.8
J
GS
= 25°C
V
= 0 V
V
GS
I
T
D
V
16
SD
J
DS
= 2 A
= 25°C
1
SAFE OPERATING AREA
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
C
) of 25°C.
Thermal
18
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1.2
MTB2P50E
20
300
250
200
150
100
50
0
1.4
5
1.6
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous I
assumed to equal the values indicated.
1000
100
Although many E−FETs can withstand the stress of
10
1.8
1
V
I
V
T
D
J
DD
GS
= 2 A
= 25°C
DM
= 250 V
= 10 V
2
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
), the energy rating is specified at rated
2.2
R
G
, GATE RESISTANCE (OHMS)
2.4
D
), in accordance with industry
10
t
f
t
r
t
t
d(on)
d(off)
D
can safely be
100