HUFA75617D3S Fairchild Semiconductor, HUFA75617D3S Datasheet
HUFA75617D3S
Specifications of HUFA75617D3S
Related parts for HUFA75617D3S
HUFA75617D3S Summary of contents
Page 1
... Peak Current vs Pulse Width Curve • UIS Rating Curve Ordering Information PART NUMBER HUFA75617D3 HUFA75617D3S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUFA75617D3ST Unless Otherwise Specified , 0.090 V 10V ...
Page 2
... Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ©2001 Fairchild Semiconductor Corporation o C, Unless Otherwise Specified SYMBOL TEST CONDITIONS 250 (Figure 11) DSS ...
Page 3
... SINGLE PULSE 0. FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 300 200 100 V = 10V GS TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION ©2001 Fairchild Semiconductor Corporation 150 175 125 o C) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT RECTANGULAR PULSE DURATION ( PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY ...
Page 4
... PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 2.5 2.0 1.5 1.0 0.5 -80 - JUNCTION TEMPERATURE ( J FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE ©2001 Fairchild Semiconductor Corporation (Continued) 100 SINGLE PULSE T = MAX RATED 100 s 10 1ms 10ms 100 200 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. ...
Page 5
... T , JUNCTION TEMPERATURE ( J FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT ©2001 Fairchild Semiconductor Corporation (Continued) 2000 1000 80 120 160 200 o C) FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ...
Page 6
... Test Circuits and Waveforms VARY t TO OBTAIN P R REQUIRED PEAK FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT g(REF) FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 18. SWITCHING TIME TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation DUT 0. DUT g(REF DUT DSS FIGURE 15. UNCLAMPED ENERGY WAVEFORMS Q g(TOT) ...
Page 7
... NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2001 Fairchild Semiconductor Corporation rev 24May 2000 DPLCAP ...
Page 8
... Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 - 6 ESG 8 EVTHRES + ...
Page 9
... Fairchild Semiconductor Corporation JUNCTION th RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 ...
Page 10
... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FAST Bottomless™ FASTr™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DenseTrench™ ...