HUFA76619D3ST Fairchild Semiconductor, HUFA76619D3ST Datasheet

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HUFA76619D3ST

Manufacturer Part Number
HUFA76619D3ST
Description
MOSFET N-CH 100V 18A DPAK
Manufacturer
Fairchild Semiconductor
Series
UltraFET™r
Datasheet

Specifications of HUFA76619D3ST

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
85 mOhm @ 18A, 10V
Drain To Source Voltage (vdss)
100V
Current - Continuous Drain (id) @ 25° C
18A
Vgs(th) (max) @ Id
3V @ 250µA
Gate Charge (qg) @ Vgs
29nC @ 10V
Input Capacitance (ciss) @ Vds
767pF @ 25V
Power - Max
75W
Mounting Type
Surface Mount
Package / Case
DPak, TO-252 (2 leads+tab), SC-63
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©2002 Fairchild Semiconductor Corporation
18A, 100V, 0.087 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFET
Packaging
Symbol
Absolute Maximum Ratings
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (R
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain Current
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Operating and Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Maximum Temperature for Soldering
NOTES:
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1. T
Continuous (T
Continuous (T
Continuous (T
Continuous (T
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Derate Above 25
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
(FLANGE)
DRAIN
J
= 25
JEDEC TO-251AA
HUFA76619D3
o
C to 150
C
C
C
C
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
= 25
= 25
= 100
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
o
C.
o
o
C, V
C, V
o
o
GS
G
C, V
C, V
SOURCE
DRAIN
= 20k ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
GS
GATE
GS
GS
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
S
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
SOURCE
T
Data Sheet
C
GATE
= 25
JEDEC TO-252AA
HUFA76619D3S
o
C, Unless Otherwise Specified
(FLANGE)
DRAIN
HUFA76619D3, HUFA76619D3S
Features
• Ultra Low On-Resistance
• Simulation Models
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Switching Time vs R
Ordering Information
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUFA76619D3ST.
HUFA76619D3
HUFA76619D3S
- r
- r
- Temperature Compensated PSPICE® and SABER™
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
PART NUMBER
Electrical Models
J
DS(ON)
DS(ON)
, T
DGR
DSS
STG
DM
pkg
GS
January 2002
D
D
D
D
D
L
= 0.085
= 0.087
HUFA76619D3, HUFA76619D3S
TO-251AA
TO-252AA
GS
Figures 6, 17, 18
V
V
PACKAGE
GS
GS
-55 to 175
Curves
Figure 4
100
100
300
260
0.5
18
18
12
12
75
16
10V
5V
HUFA76619D3, HUFA76619D3S Rev. B
76619D
76619D
BRAND
UNITS
W/
o
o
o
W
V
V
V
A
A
A
A
C
C
C
o
C

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HUFA76619D3ST Summary of contents

Page 1

... UIS Rating Curve • Switching Time vs R Ordering Information PART NUMBER HUFA76619D3 HUFA76619D3S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-252AA variant in tape and reel, e.g., HUFA76619D3ST Unless Otherwise Specified DSS DGR , T J STG January 2002 = 0 ...

Page 2

... Gate to Drain “Miller” Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ©2001 Fairchild Semiconductor Corporation o C, Unless Otherwise Specified SYMBOL TEST CONDITIONS 250 (Figure 12) DSS ...

Page 3

... SINGLE PULSE 0. FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 200 100 10V GS TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION ©2002 Fairchild Semiconductor Corporation 150 175 125 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT RECTANGULAR PULSE DURATION ( PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY V = 10V ...

Page 4

... 12A 18A GATE TO SOURCE VOLTAGE (V) GS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT ©2001 Fairchild Semiconductor Corporation (Continued) 500 100 100 s 1ms 10ms 100 200 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING 3 2.5 2 ...

Page 5

... GS 10 0.1 1 DRAIN TO SOURCE VOLTAGE (V) DS FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 200 V = 4.5V 50V 12A 160 120 GATE TO SOURCE RESISTANCE ( ) GS FIGURE 15. SWITCHING TIME vs GATE RESISTANCE ©2002 Fairchild Semiconductor Corporation (Continued 250 120 160 200 o C) FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN ISS ...

Page 6

... Test Circuits and Waveforms VARY t TO OBTAIN P R REQUIRED PEAK FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT g(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 21. SWITCHING TIME TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation DUT 0. DUT g(REF DUT DSS FIGURE 18. UNCLAMPED ENERGY WAVEFORMS Q g(TOT) ...

Page 7

... S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.3) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 ...

Page 8

... Fairchild Semiconductor Corporation DPLCAP 10 RSLC2 - 6 ESG 8 EVTHRES + ...

Page 9

... Fairchild Semiconductor Corporation JUNCTION th RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 ...

Page 10

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FAST Bottomless™ FASTr™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DenseTrench™ ...

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