74HC4052D NXP Semiconductors, 74HC4052D Datasheet
74HC4052D
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74HC4052D Summary of contents
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Dual 4-channel analog multiplexer/demultiplexer Rev. 7 — 12 January 2011 1. General description The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance with JEDEC standard ...
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... Ordering information Table 1. Ordering information Type number Package Temperature range 74HC4052 −40 °C to +125 °C 74HC4052D −40 °C to +125 °C 74HC4052DB −40 °C to +125 °C 74HC4052N −40 °C to +125 °C 74HC4052PW −40 °C to +125 °C 74HC4052BQ 74HCT4052 −40 °C to +125 °C 74HCT4052D − ...
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... NXP Semiconductors from logic Fig 3. Schematic diagram (one switch Fig 4. Functional diagram 74HC_HCT4052 Product data sheet 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer LOGIC 1-OF-4 LEVEL DECODER CONVERSION All information provided in this document is subject to legal disclaimers. Rev. 7 — 12 January 2011 nYn V CC ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74HC4052 74HCT4052 2Y0 1 2 2Y2 2Y3 2Y1 GND 8 001aah822 Fig 5. Pin configuration for DIP16, SO16 and (T)SSOP16 6.2 Pin description Table 2. Pin description Symbol Pin 2Y0 1 2Y2 2Y3 4 2Y1 GND 1Y3 11 1Y0 1Y1 14 1Y2 74HC_HCT4052 Product data sheet 74HC4052 ...
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... NXP Semiconductors 7. Functional description 7.1 Function table [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced GND (ground = 0 V). EE Symbol ...
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... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb Δt/ΔV input transition rise and fall rate 12 V GND CC (V) 8 operating area Fig 7. Guaranteed operating area as a function of the ...
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... NXP Semiconductors 10. Static characteristics Table 6. R resistance per switch for 74HC4052 and 74HCT4052 for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os − For 74HC4052: V ...
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... NXP Semiconductors Table 6. R resistance per switch for 74HC4052 and 74HCT4052 for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os − For 74HC4052: V GND or V ...
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... NXP Semiconductors Table 7. Static characteristics for 74HC4052 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. os Symbol Parameter = −40 °C to +85 °C [1] T amb ...
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... NXP Semiconductors Table 7. Static characteristics for 74HC4052 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. os Symbol Parameter I OFF-state leakage S(OFF) current I ON-state leakage ...
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... NXP Semiconductors Table 8. Static characteristics for 74HCT4052 Voltages are referenced to GND (ground = 0 V the input voltage at pins nYn or nZ, whichever is assigned as an input the output voltage at pins nZ or nYn, whichever is assigned as an output. os Symbol Parameter V LOW-level input IL voltage I input leakage current ...
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... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics for 74HC4052 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os Symbol Parameter Conditions = −40 °C to +85 °C ...
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... NXP Semiconductors Table 9. Dynamic characteristics for 74HC4052 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os Symbol Parameter Conditions t turn-off time off ...
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... NXP Semiconductors Table 10. Dynamic characteristics for 74HCT4052 GND = ns pF; for test circuit see the input voltage at a nYn or nZ terminal, whichever is assigned as an input the output voltage at a nYn or nZ terminal, whichever is assigned as an output. os Symbol Parameter Conditions = −40 °C to +125 °C ...
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... NXP Semiconductors E, Sn inputs 0.5 × V For 74HC4052 For 74HCT4052 1 Fig 14. Turn-on and turn-off times Definitions for test circuit; see R = termination resistance should be equal to the output impedance load capacitance including jig and probe capacitance load resistance Test selection switch. Fig 15. Test circuit for measuring AC performance ...
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... NXP Semiconductors Table 11. Test data Test Input PHL PLH [ PZH PHZ [ PZL PLZ [ ns; when measuring max [2] V values For 74HC4052 For 74HCT4052 12. Additional dynamic characteristics Table 12. Additional dynamic characteristics Recommended conditions and typical values; GND = the input voltage at pins nYn or nZ, whichever is assigned as an input. ...
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... NXP Semiconductors Fig 16. Test circuit for measuring sine-wave distortion V = 4.5 V; GND = Test circuit 0 iso (dB 100 10 b. Isolation (OFF-state function of frequency Fig 17. Test circuit for measuring isolation (OFF-state) 74HC_HCT4052 Product data sheet Dual 4-channel analog multiplexer/demultiplexer nYn/nZ nZ/nYn GND 0.1 F nYn/nZ nZ/nYn ...
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... NXP Semiconductors Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers G Fig 19. Test circuit for measuring crosstalk between control input and any switch 74HC_HCT4052 Product data sheet Dual 4-channel analog multiplexer/demultiplexer 0 nYn/nZ nZ/nYn GND nYn/nZ nZ/nYn V GND Sn, E nYn nZ V GND ...
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... NXP Semiconductors V = 4.5 V; GND = Test circuit (dB Typical frequency response Fig 20. Test circuit for frequency response 74HC_HCT4052 Product data sheet Dual 4-channel analog multiplexer/demultiplexer nYn/nZ nZ/nYn GND EE = −4 Ω kΩ All information provided in this document is subject to legal disclaimers. Rev. 7 — 12 January 2011 74HC4052 ...
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... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 22. Package outline SOT338-1 (SSOP16) ...
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... NXP Semiconductors DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 14. Revision history Document ID Release date 74HC_HCT4052 v.7 20110112 • Modifications: Input transition rise and fall rate corrected to family standards (errata). ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT4052 Product data sheet 74HC4052 ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 12 12 Additional dynamic characteristics ...