MT8880CE1 Zarlink, MT8880CE1 Datasheet - Page 2

• Manufacturer Part Number: MT8880CE1
• Description: DTMF TXRX 3.58MHz CMOS 5V 20-Pin PDIP Tube
• Manufacturer: Zarlink

Specifications of MT8880CE1

• Package: 20PDIP
• Operating Frequency: 3.58 MHz
• Typical Supply Current: 11 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Pin Description
14-
20
10
11
12
13
17
1
2
3
4
5
6
7
8
9
TONE
OSC1
OSC2
18-21 19-22 D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or Φ2 is low.
VRef
VSS
R/W
24
10
11
12
13
14
15
Pin #
IN+
1
2
3
4
5
6
7
GS
CS
IN-
20 PIN PLASTIC DIP/SOIC
10
28
12
13
14
15
17
18
1
2
3
4
5
6
7
8
9
1
2
4
6
7
8
9
IRQ/C
TONE Tone output (DTMF or single tone).
Name
OSC1 DTMF clock/oscillator input. Connect a 4.7 M
OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
V
R/W Read/Write input. Controls the direction of data transfer to and from the MPU and the transceiver
RS0 Register Select input. See register decode table. TTL compatible.
IN+ Non-inverting op-amp input.
V
IN- Inverting op-amp input.
GS
CS
Φ2
P
Ref
SS
20
19
18
17
16
15
14
13
12
11
Gain Select. Gives access to output of front end differential amplifier for connection of feedback
resistor.
Reference Voltage output, nominally V
Ground input (0 V).
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
registers. TTL compatible.
Chip Select, TTL input (CS=0 to select the chip).
System Clock input. TTL compatible. N.B. Φ2 clock input need not be active when the device
is not being accessed.
Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has been
selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal representative
of the input signal applied at the input op-amp. The input signal must be within the bandwidth
limits of the call progress filter. See Figure 8.
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
Φ2
RS0
OSC1
OSC2
TONE
VRef
VSS
R/W
IN+
NC
NC
GS
CS
IN-
Figure 2 - Pin Connections
Zarlink Semiconductor Inc.
10
11
12
1
2
3
4
5
6
7
8
9
24 PIN SSOP
MT8880C
2
24
23
22
21
20
19
18
17
16
15
14
13
DD
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
Φ2
RS0
Description
/2 is used to bias inputs at mid-rail (see Fig. 13).
Ω
resistor to VSS if crystal oscillator is used.
OSC1
OSC2
VRef
VSS
NC
NC
NC
5
6
7
8
9
10
11
28 PIN PLCC
•
25
24
23
22
21
20
19
Data Sheet
NC
NC
NC
D3
D2
D1
D0