MT8880CE1 Zarlink, MT8880CE1 Datasheet - Page 21

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MT8880CE1

Manufacturer Part Number
MT8880CE1
Description
DTMF TXRX 3.58MHz CMOS 5V 20-Pin PDIP Tube
Manufacturer
Zarlink
Datasheet

Specifications of MT8880CE1

Package
20PDIP
Operating Frequency
3.58 MHz
Typical Supply Current
11 mA
Typical Operating Supply Voltage
5 V
Minimum Operating Supply Voltage
4.75 V
Maximum Operating Supply Voltage
5.25 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT8880CE1
Manufacturer:
Zarlink
Quantity:
2
Part Number:
MT8880CE1
Manufacturer:
ZARLINK
Quantity:
20 000
AC Electrical Characteristics
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
* The data bus output buffers are no longer sourcing or sinking current by t
#
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
See Figure 6 regarding guard time adjustment.
M
M
O
N
O
U
U
N
A
D
K
T
E
T
P
T
E
R
F
C
E
T
F
C
L
I
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause=40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz (
9) For an error rate of less than 1 in 10,000.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) Referenced to the minimum valid accept level.
12) For guard time calculation purposes.
High group output level
Low group output level
Pre-emphasis
Output distortion (Single Tone)
Frequency deviation
Output load resistance
Φ2 cycle period
Φ2 high pulse width
Φ2 low pulse width
Φ2 rise and fall time
Address, R/W hold time
Address, R/W setup time (before Φ2)
Data hold time (read)
Φ2 to valid data delay (read)
Data setup time (write)
Data hold time (write)
Input Capacitance (data bus)
Output Capacitance (IRQ/CP)
Crystal/clock frequency
Clock input rise time
Clock input duty cycle
Clock input duty cycle
Capacitive load (OSC2)
°
C and for design aid only: not guaranteed and not subject to production testing.
Characteristics
±
- Voltages are with respect to ground (V
1.5%
±
2 Hz.
Zarlink Semiconductor Inc.
t
MT8880C
t
AH,
V
V
AS,
t
t
DC
C
Sym.
t
THD
t
t
t
t
t
LHCL
HLCL
C
dB
DHW
HOUT
R
DSW
C
LOUT
CYC
t
DHR
DDR
t
R,
OUT
±
f
f
CH
CL
t
t
LO
D
LT
IN
C
RWH
RWS
2%).
CL
P
t
DHR
F
21
.
3.5759 3.5795 3.5831
Min.
-6.1
-8.1
10
26
23
22
45
10
40
0
SS
) unless otherwise stated.
Typ.
±0.7
250
115
110
-35
50
2
5
5
Max.
±1.5
-2.1
-4.1
100
110
110
50
25
60
30
3
Units
MHz
dBm
dBm
kΩ
dB
dB
pF
pF
pF
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
R
R
R
25 kHz Bandwidth
R
f
*
200 pF load
Ext. clock
Ext. clock
Ext. clock
C
L
L
L
L
=3.579545 MHz
=10 kΩ
=10 kΩ
=10 kΩ
=10 kΩ
Conditions
Data Sheet

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