72T18125L5BBI Integrated Device Technology (Idt), 72T18125L5BBI Datasheet

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72T18125L5BBI

Manufacturer Part Number
72T18125L5BBI
Description
FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 512K x 18/1M x 9 240-Pin BGA
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.IDT72T1845L6-7BB.pdf (55 pages)

Specifications of 72T18125L5BBI

Package
240BGA
Configuration
Dual
Bus Directional
Uni-Directional
Density
9 Mb
Organization
512Kx18|1Mx9
Data Bus Width
9/18 Bit
Timing Type
Asynchronous|Synchronous
Expansion Type
Depth|Width
Typical Operating Supply Voltage
2.5 V
Operating Temperature
-40 to 85 °C
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEATURES:
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FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Choose among the following memory organizations:
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
IDT72T1895
IDT72T18105 ⎯ ⎯ ⎯ ⎯ ⎯
IDT72T18115 ⎯ ⎯ ⎯ ⎯ ⎯
IDT72T18125 ⎯ ⎯ ⎯ ⎯ ⎯
WHSTL
RHSTL
ASYW
SHSTL
TRST
MRS
PRS
TMS
TDO
TCK
Vref
OW
TDI
BE
IW
IP
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
2,048 x 18/4,096 x 9
4,096 x 18/8,192 x 9
8,192 x 18/16,384 x 9
16,384 x 18/32,768 x 9
32,768 x 18/65,536 x 9
65,536 x 18/131,072 x 9
131,072 x 18/262,144 x 9
262,144 x 18/524,288 x 9
524,288 x 18/1,048,576 x 9
(BOUNDARY SCAN)
WCS
CONFIGURATION
WRITE CONTROL
JTAG CONTROL
WRITE POINTER
CONTROL
CONTROL
2.5 VOLT HIGH-SPEED TeraSync™ FIFO
18-BIT/9-BIT CONFIGURATIONS
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9,
16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9
RESET
HSTL I/0
LOGIC
LOGIC
WEN WCLK/WR
LOGIC
BUS
OE
524,288 x 18 or 1,048,576 x 9
131,072 x 18 or 262,144 x 9
262,144 x 18 or 524,288 x 9
OUTPUT REGISTER
65,536 x 18 or 131,072 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
8,192 x 18 or 16,384 x 9
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
D
INPUT REGISTER
Q
0
0
RAM ARRAY
-D
-Q
n
n
(x18 or x9)
(x18 or x9)
1
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Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)
PlasticBall Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts are available, see ordering information
OFFSET REGISTER
READ POINTER
EREN
LOGIC
ERCLK
CONTROL
FLAG
LOGIC
READ
LD
SEN
RCLK/RD
RCS
REN
SCLK
5909 drw01
MARK
ASYR
IDT72T18105, IDT72T18115
RT
FEBRUARY 2009
PAF
FWFT/SI
FSEL1
FF/IR
EF/OR
PAE
HF
PFM
FSEL0
IDT72T1845, IDT72T1855
IDT72T1865, IDT72T1875
IDT72T1885, IDT72T1895
IDT72T18125
DSC-5909/19

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72T18125L5BBI Summary of contents

Page 1

VOLT HIGH-SPEED TeraSync™ FIFO 18-BIT/9-BIT CONFIGURATIONS 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9, 131,072 x 18/262,144 ...

Page 2

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 PIN CONFIGURATIONS A1 BALL PAD CORNER A WCS PRS LD B MRS WCLK FWFT/SI C WEN WHSTL V DDQ D ASYW SEN V DDQ E IW SCLK ...

Page 3

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 PIN CONFIGURATIONS (CONTINUED) A1 BALL PAD CORNER ...

Page 4

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 DESCRIPTION: The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/ 72T18105/72T18115/72T18125 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. ...

Page 5

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 The device can be configured with different input and output bus widths as shown in Table 1. A Big-Endian/Little-Endian data word format is provided. This function is ...

Page 6

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 WRITE CLOCK (WCLK/WR) WRITE ENABLE (WEN) WRITE CHIP SELECT (WCS) (x18, x9) DATA IN (D SERIAL CLOCK (SCLK) SERIAL ENABLE(SEN) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) ...

Page 7

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 PIN DESCRIPTION Symbol Name I/O TYPE ASYR (1) Asynchronous LVTTL Read Port INPUT ASYW (1) Asynchronous LVTTL Write Port INPUT BE (1) Big-Endian/ LVTTL Little-Endian INPUT D ...

Page 8

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 PIN DESCRIPTION (CONTINUED) Symbol Name I/O TYPE PRS HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During ...

Page 9

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 PIN DESCRIPTION (CONTINUED) Symbol Name I/O TYPE WHSTL (1) Write Port HSTL LVTTL Select INPUT V +2.5V Supply I CC GND Ground Pin I Vref Reference I ...

Page 10

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTES: 1. Stresses greater than ...

Page 11

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 DC ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.125V 0°C to +70°C;Industrial Symbol Parameter I Input Leakage Current LI I Output Leakage ...

Page 12

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 AC ELECTRICAL CHARACTERISTICS = 2.5V ± 5%, T (Commercial 0°C to +70°C;Industrial Symbol Parameter f Clock Cycle Frequency (Synchronous Data ...

Page 13

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 AC ELECTRICAL CHARACTERISTICS ⎯ ASYNCHRONOUS TIMING = 2.5V ± 5%, T (Commercial 0°C to +70°C;Industrial Symbol Parameter f Cycle Frequency (Asynchronous) A ...

Page 14

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 HSTL 1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels NOTE 1.5V±. DDQ EXTENDED HSTL 1.8V ...

Page 15

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 OUTPUT ENABLE & DISABLE TIMING Output Enable & Output V CC Normally 2 LOW 100mV 100mV Output V CC Normally 2 HIGH NOTES: 1. ...

Page 16

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/ 72T18105/72T18115/72T18125 support two different timing modes of opera- tion: IDT Standard mode ...

Page 17

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 (4,097-m) writes for the IDT72T1855, (8,193-m) writes for the IDT72T1865, (16,385-m) writes for the IDT72T1875, (32,769-m) writes for the IDT72T1885, (65,536-m) writes for the IDT72T1895, (131,073-m) writes ...

Page 18

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE IDT72T1845 IW = x18 or IDT72T1845 IDT72T1855 OW = x18 0 Number of ...

Page 19

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 LD WEN REN SEN WCLK RCLK ...

Page 20

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 1st Parallel Offset Write/Read Cycle D/Q8 EMPTY OFFSET REGISTER 2nd Parallel Offset Write/Read Cycle D/Q8 EMPTY OFFSET REGISTER ...

Page 21

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination ...

Page 22

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 or both together. When REN and LD are restored to a LOW level, reading of the offset registers continues where it left off. It should be noted, ...

Page 23

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 18-bit wide data ( data inputs for 9-bit wide ...

Page 24

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 The MARK input must remain HIGH during the whole period of retransmit mode, a falling edge of RCLK while MARK is LOW will take the device out ...

Page 25

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 OUTPUT ENABLE ( OE ) When Output Enable is enabled (LOW), the parallel output buffers receive data from the output register. When OE is HIGH, the output ...

Page 26

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 programming of the offsets. (D becomes a valid bit). Additionally, output Q 8 become a valid bit when performing a read of the offset register. IP mode ...

Page 27

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 If asynchronous PAE configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH on the ...

Page 28

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...

Page 29

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 JTAG TIMING SPECIFICATION t 1 TCK t 3 TDI/ TMS TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t (1) ...

Page 30

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72T1845/72T1855/ 72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/72T18125 in- corporates the necessary ...

Page 31

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 1 0 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically reset upon ...

Page 32

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction is used ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects the one-bit ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS FSEL0, FSEL1 t RSS OW HRSS WHSTL t HRSS RHSTL ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF NOTE: 1. During Partial ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 NO WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN t ENS RCS ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 RCLK t ENS REN t ENS t ENH RCS RCSLZ LAST DATA WCLK WEN Dn NOTES: is the minimum time ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERCIAL AND INDUSTRIAL 2Kx18/4Kx9, 4Kx18/ 38 TEMPERATURE RANGES FEBRUARY 10, 2009 ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERCIAL AND INDUSTRIAL 2Kx18/4Kx9, 4Kx18/ 39 TEMPERATURE RANGES FEBRUARY 10, 2009 ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERCIAL AND INDUSTRIAL 2Kx18/4Kx9, 4Kx18/ 40 TEMPERATURE RANGES FEBRUARY 10, 2009 ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERCIAL AND INDUSTRIAL 2Kx18/4Kx9, 4Kx18/ 41 TEMPERATURE RANGES FEBRUARY 10, 2009 ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERCIAL AND INDUSTRIAL 2Kx18/4Kx9, 4Kx18/ 42 TEMPERATURE RANGES FEBRUARY 10, 2009 ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERCIAL AND INDUSTRIAL 2Kx18/4Kx9, 4Kx18/ 43 TEMPERATURE RANGES FEBRUARY 10, 2009 ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 t SCLK t t SCKH SCKL SCLK t t SENS SEN t t LDS LD t SDS BIT 1 SI NOTES mode: X ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 t t CLKL CLKL WCLK t t ENS ENH WEN PAF +1) words in FIFO RCLK REN NOTES PAF offset . ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 WCLK WEN words in FIFO PAF RCLK REN NOTES PAF offset maximum FIFO depth. In IDT ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 WCLK WEN D/2 words in FIFO HF D RCLK REN NOTES IDT Standard mode maximum FIFO depth. If x18 ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERCIAL AND INDUSTRIAL 2Kx18/4Kx9, 4Kx18/ 48 TEMPERATURE RANGES FEBRUARY 10, 2009 ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 WCLK t ENS WEN n+1 n+2 t SKEW1 RCLK a t ERCLK ERCLK REN RCS EREN ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 RCLK REN FFA NOTE LOW, WEN = LOW and RCS = LOW. Figure ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 No Write WCLK 1 WEN SKEW t CYL Last Word W X NOTES LOW, RCS = LOW ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 t CYC t t CYH CYL Last Word in O/P Register t RPE t EFA EF NOTES ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any ...

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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 FWFT/SI FWFT/SI WRITE CLOCK WCLK IDT 72T1845 WRITE ENABLE WEN 72T1855 72T1865 INPUT READY 72T1875 IR 72T1885 72T1895 72T18105 n 72T18115 DATA IN Dn 72T18125 4,096 x ...

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ORDERING INFORMATION XXXXX Device Type Power Speed Package NOTES: 1. Industrial temperature range product for 5ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts available. ...

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