M29DW128G70NF6E NUMONYX, M29DW128G70NF6E Datasheet - Page 16

• Manufacturer Part Number: M29DW128G70NF6E
• Description: P7ED TSOP56 DUAL BANK
• Manufacturer: NUMONYX

Bus operations
3
3.1
3.2
3.3
3.4
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Bus operations
There are five standard bus operations that control the device. These are bus read (random
and page modes), bus write, output disable, standby and automatic standby.
Dual operations are possible in the M29DW128G, thanks to its multiple bank architecture.
While programming or erasing in one bank, read operations are possible in any of the other
banks. Write operations are only allowed in one bank at a time.
See
enable, write enable, and reset pins are ignored by the memory and do not affect bus
operations.
Bus read
Bus read operations read from the memory cells, or specific registers in the command
interface. To speed up the read operation the memory array can be read in page mode
where data is internally read and stored in a page buffer. The page has a size of 8 words
and the specific word inside the page is addressed by the address inputs A0-A2.
A valid bus read operation involves setting the desired address on the address inputs,
applying a Low signal, V
High, V
waveforms,
details of when the output becomes valid.
Bus write
Bus write operations write to the command interface. A valid bus write operation begins by
setting the desired address on the address inputs. The address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole bus write operation. See
waveforms
requirements.
Output disable
The data inputs/outputs are in the high impedance state when output enable is High, V
Standby
Driving Chip Enable High, V
and the data inputs/outputs pins are placed in the high-impedance state. To reduce the
supply current to the standby supply current, I
V
CC
Table 4: Bus operations
± 0.3 V. For the standby current level see
IH
. The data inputs/outputs will output the value, see
and
Figure 14: Page read AC
Table 24
IL
and
, to Chip Enable and Output Enable and keeping Write Enable
IH
for a summary. Typical glitches of less than 5 ns on chip
Table
, in read mode, causes the memory to enter standby mode
25, Write AC characteristics, for details of the timing
waveforms, and
Figure 15: Write enable controlled program
CC2
Table 22: DC
, Chip Enable should be held within
Table 23: Read AC
characteristics.
Figure 13: Random read AC
characteristics, for
M29DW128G
IH
IH
.
,