M29DW128G70NF6E NUMONYX, M29DW128G70NF6E Datasheet - Page 26

• Manufacturer Part Number: M29DW128G70NF6E
• Description: P7ED TSOP56 DUAL BANK
• Manufacturer: NUMONYX

Command interface
7.1.6
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blocks. Each additional block must therefore be selected within the timeout period of the last
block. The timeout timer restarts when an additional block is selected. After the sixth bus
write operation, a bus read operation outputs the status register (bus reading operations
from banks different from those including the blocks being erased, output the memory array
content). See
identify if the program/erase controller has started the block erase operation.
After the block erase operation has completed, the memory returns to the read mode,
unless an error has occurred. When an error occurs, bus read operations will continue to
output the status register. A Read/Reset command must be issued to reset the error
condition and return to read mode.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the block erase operation appears to
start but will terminate within about 100 µs, leaving the data unchanged. No error condition
is given when protected blocks are ignored.
During the block erase operation the memory ignores all commands except the Erase
Suspend command and the Read/Reset command which is only accepted during the
timeout period. Typical block erase time and block erase timeout are given in
The block erase operation is aborted by performing a reset or powering down the device. In
this case, data integrity cannot be ensured, and it is recommended to erase again the blocks
aborted.
Erase Suspend command
The Erase Suspend command can be used to temporarily suspend a block erase operation.
One bus write operation is required to issue the command together with the block address.
After the command sequence is written, a minimum block erase timeout occurs (see
Section 7.1.6: Erase Suspend
addresses and block erase commands can be written.
The program/erase controller suspends the erase operation within the erase suspend
latency time of the Erase Suspend command being issued. However, when the Erase
Suspend command is written during the block erase timeout, the device immediately
terminates the timeout period and suspends the erase operation.
Once the program/erase controller has stopped, the memory operates in read mode and the
erase is suspended.
During erase suspend it is possible to read and execute program or write to buffer program
operations in blocks that are not suspended; both read and program operations behave as
normal on these blocks. Reading from blocks that are suspended will output the status
register. If any attempt is made to program in a protected block or in the suspended block
then the Program command is ignored and the data remains unchanged. In this case the
status register is not read and no error condition is given.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an erase suspend. The Read/Reset command must be issued to return the device to
read array mode before the Resume command will be accepted.
During erase suspend a bus read operation to the extended memory block will output the
extended memory block data. Once in the extended block mode, the Exit Extended Block
command must be issued before the erase operation can be resumed.
The Erase Suspend command is ignored if written during chip erase operations.
Figure 15: Write enable controlled program waveforms
command). During the timeout period, additional block
for details on how to
Table
M29DW128G
12.